Semiconductor Trench Layout for Single-Step Dual-Depth Etching

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Solution Overview

Problem

Existing manufacturing methods for semiconductor devices, particularly vertical trench MOSFETs, face inefficiencies in forming multiple types of trench structures simultaneously, leading to increased manufacturing steps and complexity.

Innovation Solution

A method where trench structures of differing depths are formed simultaneously by controlling etching rates through anisotropic etching and oblique ion implantation, allowing for the concurrent creation of shallow and deep trench isolation structures without additional steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional manufacturing methods are used to form multiple types of trench structures, then manufacturing precision is maintained, but the number of manufacturing steps increases and productivity decreases

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidnumber of manufacturing steps
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent combines the formation of shallow trenches and deep trenches into a single etching step by using a dual-layer mask structure. The first mask layer and second mask layer are patterned to define both shallow trench regions and deep trench regions simultaneously, allowing one etching process to create multiple trench types with different depths, thereby reducing the total number of manufacturing steps and improving productivity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the mask structure into multiple layers (first mask layer and second mask layer) with different etch selectivities. This segmentation allows different regions of the substrate to receive different etching depths in the same process step, enabling the simultaneous formation of shallow trenches (stopped at the first mask layer) and deep trenches (penetrating through both mask layers) without requiring separate etching steps

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If multiple etching steps are used to form trenches of different depths, then manufacturing precision is improved, but manufacturing time increases and productivity decreases

Engineering Contradiction:
Improvetrench depth controlVSAvoidmanufacturing cycle time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent changes the etching parameters dynamically within a single etching step by utilizing the different etch selectivities of the first mask layer and second mask layer. The etching process is controlled to stop at different depths in different regions based on the mask layer composition and thickness, achieving precise depth control for both shallow and deep trenches simultaneously without requiring multiple sequential etching steps, thus reducing manufacturing cycle time while maintaining precision

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables efficient manufacturing of semiconductor devices with multiple trench structures, reducing the number of manufacturing steps and enhancing production efficiency.

Implementation Method 1

controlling etching rates through anisotropic etching

Methodology Applied
Scientific EffectAnisotropic etching:

Implementation Method 2

controlling etching rates through anisotropic etching and oblique ion implantation

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20260013195A1Manufacturing method of semiconductor device and semiconductor device
Publication Date: 2026.01.08 ROHM CO LTD
  • US20260013195A1 patent drawing
  • US20260013195A1 patent drawing
  • US20260013195A1 patent drawing

AI summary

A manufacturing method of a semiconductor device includes forming a semiconductor layer of a first conductivity type that is located on a substrate, simultaneously forming a first trench having the semiconductor layer as a bottom surface and a second trench that runs through the semiconductor layer, simultaneously forming an insulator that fills up the first trench and an insulating layer that covers the second trench, removing a part of the insulator such that the bottom surface of the first trench is not exposed, removing a part of the insulating layer such that the semiconductor substrate is exposed in the second trench, embedding in the first trench a first conductor that is separated from the semiconductor layer, and embedding in the second trench a second conductor that is in contact with the semiconductor substrate. A width of the second trench is greater than a width of the first trench.