Semiconductor Structure Dual Dielectric Layers Field Oxide Edge

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Solution Overview

Problem

Designing a metal oxide semiconductor (MOS) device that achieves high off-state breakdown voltage while maintaining low on-state resistance is challenging, as increasing off-state breakdown voltage tends to increase on-state resistance, making it difficult to optimize both parameters simultaneously.

Innovation Solution

The semiconductor structure incorporates two dielectric layers of different thicknesses, with a thicker first dielectric layer covering the edge portion of the field oxide to reduce the hot carrier effect and prevent breakdown phenomena, allowing for enhanced breakdown voltage and controlled on-state resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the off-state breakdown voltage is increased, then the high voltage operation capability is improved, but the on-state resistance comparatively increases

Engineering Contradiction:
Improveoff-state breakdown voltageVSAvoidon-state resistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by creating a non-uniform dielectric structure where the first dielectric layer has a greater thickness at the edge portion of the field oxide compared to the center region. This localized thickness variation allows the edge region to have higher breakdown strength where electric field concentration occurs, while the center region maintains lower resistance for current flow, thus resolving the contradiction between high breakdown voltage and low on-state resistance

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the physical parameter of dielectric layer thickness from a uniform value to a graded value, with the first dielectric layer thickness increasing toward the field oxide edge. This parameter modification allows optimization of the electric field distribution, enabling higher overall breakdown voltage while maintaining acceptable on-state resistance through controlled field concentration at specific locations

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If a single uniform dielectric layer is used, then the manufacturing process is simple, but the hot carrier effect and breakdown phenomena occur at the field oxide edge

Engineering Contradiction:
Improvedielectric layer fabricationVSAvoidbreakdown voltage
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the dielectric layer into two distinct layers: a first dielectric layer with greater thickness covering the field oxide edge, and a second dielectric layer with smaller thickness in the center region. This segmentation allows each layer to perform its specific function - the first layer protects against hot carrier effects at the edge, while the second layer maintains proper electrical characteristics in the channel region, thereby improving reliability without significantly complicating manufacturing

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dimensional variation in the dielectric layer thickness along the vertical dimension, creating a graded thickness profile rather than a uniform structure. This dimensional change allows the dielectric layer to provide enhanced protection at the field oxide edge where it is thickest, while maintaining appropriate electrical properties in other regions, thus resolving the contradiction between manufacturing simplicity and breakdown resistance

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9082787B2Semiconductor structure and manufacturing process thereof
Publication Date: 2015.07.14 MACRONIX INTERNATIONAL CO LTD
  • US9082787B2 patent drawing
  • US9082787B2 patent drawing
  • US9082787B2 patent drawing

AI summary

A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.