Semiconductor Device Singulation via Dual Etching
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Solution Overview
Problem
Current semiconductor device manufacturing processes face challenges in efficiently singulating chip regions while maintaining the integrity of metal bumps and passivation stacks, leading to complexities in processing and manufacturing due to the need for precise etching and material selection.
Innovation Solution
A method involving the formation of passivation stacks with specific material layers and patterning processes to create openings and recesses for metal bumps, followed by bonding with a second substrate and using an etch gas to remove oxide layers, allowing for effective singulation of chip regions without damaging the metal bumps or passivation stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional etching processes are used for singulation, then chip regions can be separated, but the metal bumps and passivation stacks are damaged due to prolonged etching time
Solution Approach 1:
The patent segments the etching process into two distinct stages: a first etching process that removes oxide layers and exposes metal bumps without damaging them, and a second etching process that completes the singulation. This segmentation allows each process to be optimized independently, preventing damage while achieving efficient separation.
Solution Approach 2:
The patent changes etching parameters between the two processes - using different etching gases, power levels, and pressure conditions. The first process uses parameters optimized for selective oxide removal with short etching time, while the second process uses parameters optimized for complete singulation. This parameter variation enables efficient singulation without damaging sensitive structures.
2Manufacturing precision
If etching time is extended to ensure complete singulation, then chip regions are fully separated, but the etching window narrows and damage to metal bumps occurs
Solution Approach 1:
The first etching process performs preliminary action by removing oxide layers and exposing metal bumps before the second etching process completes the singulation. This preliminary exposure allows the second process to focus solely on separation without needing extended time that would cause damage, effectively widening the etching window.
Solution Approach 2:
The patent introduces an intermediary step where metal bumps are exposed and potentially reflowed before final singulation. This intermediary state facilitates cleaner separation in the second etching process, achieving complete singulation with reduced etching time and minimized damage risk.
3Reliability
If precise etching control is implemented to protect metal bumps, then damage is prevented, but processing complexity increases
Solution Approach 1:
The patent applies homogeneous etching conditions within each of the two processes, using uniform gas flows and power distribution. This homogeneity simplifies process control within each stage, making the overall complex two-stage process easier to implement and reproduce compared to attempting single-stage precise control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient singulation of chip regions with reduced etching time and improved etching windows, preventing damage to the metal bumps and passivation stacks, thus enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
an etch gas to remove oxide layers
Data Source
AI summary
A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.