Semiconductor Device Dual Gate D/A Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The demand for higher image quality in semiconductor devices requires a reduction in the size and cost while maintaining or increasing the number of gray levels, which is challenging due to the need for a large number of gray level power supply lines in existing OLED display devices.
Innovation Solution
A semiconductor device with a transistor having overlapping gates and a dual D/A converter system that reduces the number of gray level power supply lines by using 2N−k and 2k lines instead of 2N, allowing for 2N gray levels, thereby minimizing the device size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of gray level power supply lines is increased to achieve higher gray levels, then image quality is improved, but device size increases
Solution Approach 1:
The patent divides the gray level control into two independent gate systems: first gate for coarse gray level selection (2^(N-k) levels) and second gate for fine gray level adjustment (2^k levels). This segmentation allows the total gray level (2^N) to be achieved without requiring 2^N power supply lines, thereby reducing device area while maintaining image quality
Solution Approach 2:
The patent transitions from a single-dimensional gray level control (one gate with 2^N levels requiring 2^N power lines) to a two-dimensional control space (two gates with 2^(N-k) and 2^k levels respectively). This dimensional change enables gray level representation through coordinate-like combination of two smaller sets, reducing the number of required power supply lines from 2^N to 2^(N-k) + 2^k
2Measurement precision
If the number of gray level power supply lines is increased to achieve higher gray levels, then image quality is improved, but manufacturing cost increases
Solution Approach 1:
By segmenting gray level control into two independent gate systems with fewer power supply lines each (2^(N-k) and 2^k instead of 2^N), the patent reduces the complexity of power supply network routing and connection, thereby lowering manufacturing cost while maintaining 2^N gray level precision
Solution Approach 2:
The patent changes the parameter of power supply line count from 2^N to 2^(N-k) + 2^k by introducing a new control parameter k, which optimizes the balance between gray level precision and manufacturing complexity, reducing both device size and manufacturing cost
3Area of stationary object
If the number of gray level power supply lines is reduced, then device size is decreased, but gray level control capability is compromised
Solution Approach 1:
The patent compensates for reduced power supply lines by adding another dimension of control through the second gate. Instead of using 2^N lines for one gate, it uses 2^(N-k) lines for first gate plus 2^k lines for second gate, where the combination of both gates reconstructs the full 2^N gray level capability
Solution Approach 2:
The patent merges the control functions of two independent gate systems into a unified gray level control mechanism. The first gate controls the major gray level segments while the second gate controls the minor adjustments within each segment, and their combined effect achieves the full gray level range with fewer total power supply lines
Data Source
AI summary
A semiconductor device includes a transistor including a first gate (front gate) and a second gate (back gate) overlapping with each other with a semiconductor film therebetween, and a display element. The transistor and the display element are electrically connected to each other. The first gate is supplied with one of 2N−k potentials. The second gate is supplied with one of 2k potentials. One of 2N−k potentials and one of 2k potentials are obtained in such a manner that N-bit digital data is divided into (N−k)-bit digital data and k-bit digital data and they are subjected to D/A conversion. At this time, the total number of gray level power supply lines used for D/A conversion is equal to the sum of 2N−k and 2k. This is smaller than 2N, which the total number of the gray level power supply lines usually needed for D/A conversion of N-bit digital data.