Semiconductor Device With Dual-Gate Oxide Transistor
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Solution Overview
Problem
Current semiconductor devices face challenges in maintaining data storage without power, with volatile memory devices requiring frequent refresh operations and nonvolatile memory devices experiencing degradation due to tunneling current, and multilevel memories encountering issues with circuit size, cost, and data integrity.
Innovation Solution
A semiconductor device utilizing a dual-gate transistor with an oxide semiconductor layer, which reduces off-state current and allows for stable data storage and retrieval using a reference potential circuit, eliminating the need for frequent refresh operations and reducing circuit size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a volatile memory device (DRAM) is used to store data, then writing and reading operations are fast, but refresh operations are required frequently due to charge leakage, increasing power consumption
Solution Approach 1:
The patent changes the fundamental parameter of charge storage from transient capacitor charge (DRAM) to stable trapped charge in a charge trap layer, enabling nonvolatile storage without requiring refresh operations, thus eliminating the power consumption issue while maintaining fast access speeds
2Duration of action of stationary object
If a nonvolatile memory device (flash memory) is used to store data, then data holding period is extended and refresh operation is not needed, but the gate insulating layer deteriorates due to tunneling current during writing operations
Solution Approach 1:
The patent introduces a charge trap layer as an intermediary between the control gate and the channel, which traps charge without requiring high-voltage tunneling through the gate insulating layer. This mediator enables nonvolatile storage while protecting the gate insulating layer from deterioration
Solution Approach 2:
The patent changes the charge storage mechanism from tunneling-based (flash memory) to field-effect-based charge trapping, operating at lower voltages and avoiding the high electric fields that cause gate insulating layer breakdown, thus improving reliability
3Quantity of substance
If a multilevel memory is used to increase storage capacity, then more data can be stored per cell, but the number of required circuits increases, enlarging device size and cost
Solution Approach 1:
The patent makes a single memory cell structure universally applicable for both binary and multilevel storage by controlling the amount of charge trapped in the charge trap layer, allowing one structure to perform multiple storage functions without increasing circuit complexity
4Measurement precision
If verification operation is performed in multilevel memory to ensure data integrity, then data reading accuracy improves, but the threshold potential margin decreases, causing wrong data reading
Solution Approach 1:
The patent changes the verification mechanism by adjusting the potential of the control gate to create sufficient margin between the verification threshold and the data storage levels, ensuring that verification can be performed accurately without causing charge discharge that would lead to wrong data reading
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device enables long-term data storage without power, reduces circuit size and power consumption, and enhances data reliability by using a dual-gate transistor with an oxide semiconductor layer, allowing for high-speed operations and unlimited writing operations without degradation.
Implementation Method 1
a transistor included in a memory element has leakage current (off-state current) between a source and a drain in an off state
Data Source
AI summary
One object is to provide a novel semiconductor device which can hold stored data even when not powered and which has an unlimited number of writing operations. Another object is to reduce a circuit size and to improve reliability of writing and reading of data. When a memory cell using a transistor including an oxide semiconductor layer is subjected to the verification operation and reading of data, a dual-gate transistor showing different threshold voltages is used as a resistor; thus, stable verification operation and reading operation can be performed by only a reference potential circuit.