Semiconductor Component Dual-Layer Trace Routing
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Solution Overview
Problem
Conventional semiconductor components require multiple high-resistance conductor layers for wiring, leading to poor electrical characteristics due to wider traces and increased parasitic capacitors.
Innovation Solution
A semiconductor component design that uses only two conductor layers to implement crossings of multiple traces, eliminating the need for high-resistance layers by strategically arranging continuous segments across layers via through structures like vias, allowing traces to cross each other while maintaining low resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple high-resistance conductor layers are used for wiring, then trace crossings can be implemented, but resistance and parasitic capacitance increase leading to poor electrical characteristics
Solution Approach 1:
The patent transitions from using multiple conductor layers (vertical dimension) to using a single planar conductor layer with spiral/meander patterns (horizontal dimension). Traces that would traditionally cross in different layers are instead routed through continuous spiral patterns within the same layer, eliminating the need for high-resistance upper layers while maintaining crossing functionality.
Solution Approach 2:
The patent divides continuous traces into multiple spiral or meander segments within a single conductor layer. Each spiral segment serves as a continuous trace path, allowing multiple traces to coexist and cross in the planar domain without requiring additional conductor layers, thus reducing overall resistance and parasitic capacitance.
2Power
If wider traces are used to withstand high currents in high-resistance layers, then current carrying capacity improves, but parasitic capacitance increases resulting in poor electrical characteristics
Solution Approach 1:
The patent moves trace routing from the vertical dimension (multiple layers) to the horizontal dimension (spiral patterns in single layer). This allows traces to maintain optimal width for current carrying while reducing parasitic capacitance by eliminating overlapping structures between layers, thereby improving electrical characteristics without sacrificing power handling.
3Adaptability or versatility
If multiple conductor layers are used to implement crossed traces, then wiring flexibility improves, but device complexity increases
Solution Approach 1:
The patent resolves the contradiction by utilizing planar spiral patterns within a single conductor layer to achieve what would traditionally require multiple layers. The spiral geometry provides the necessary routing flexibility and trace crossings without increasing vertical complexity, thereby simplifying the device structure while maintaining wiring adaptability.
Data Source
AI summary
An integrated circuit is provided. The integrated circuit includes a first trace, a second trace and a third trace. The first trace, the second trace and the third trace are each a continuous trace. The first trace, the second trace and the third trace together use only two conductor layers of a semiconductor structure. In a crossing area of the first trace, the second trace and the third trace, the first trace crosses the second trace once, the first trace crosses the third trace once, and the second trace crosses the third trace once.