Semiconductor Device With Dual Metallization Stacks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices with photonic and electronic functionality face limitations in stack density and signal transfer speed due to parasitic capacitances and resistances, particularly in on-chip optical signal processing.
Innovation Solution
A semiconductor device with a dual metallization stack structure, where electrically insulating layers are directly bonded without intermediate materials, allowing for increased optical and electronic component density and improved signal transfer by embedding optical waveguides within insulating layers, and connecting metallization layers through direct bonding methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal pads and bump bonding techniques are used to mount CMOS chips on silicon-on-insulator wafers, then electrical connections are established, but stack density is limited and parasitic capacitances and resistances increase
Solution Approach 1:
The patent merges photonic and electronic functionalities into a single integrated device structure. The CMOS chip and silicon-on-insulator wafer are bonded together to form a unified stack where optical waveguides and electronic circuitry coexist and interact, eliminating the need for separate mounting processes and reducing overall system complexity.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional vertical stacking. Multiple functional layers (CMOS circuitry, optical waveguides, photodetectors, microlenses) are arranged in vertical tiers,充分利用 the third dimension to increase component density while maintaining electrical and optical performance.
2Productivity
If traditional bonding techniques are used, then electrical connections are made, but signal transfer speed is reduced due to parasitic effects
Solution Approach 1:
The patent extracts and eliminates intermediate bonding materials and complex interconnection structures that generate parasitic effects. By using direct wafer bonding techniques and minimizing the number of interfaces between layers, the design removes sources of parasitic capacitance and resistance, enabling faster signal transfer.
Solution Approach 2:
The patent introduces optimized intermediary structures such as thin dielectric layers and carefully designed metallization schemes that mediate between different functional layers. These intermediaries are engineered to minimize parasitic effects while maintaining necessary electrical and mechanical connections.
3Adaptability or versatility
If a dense stack of optical and electrical components is implemented, then on-chip optical signal processing capability is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the device into distinct functional modules (CMOS processing layer, optical waveguide layer, photodetector layer, microlens layer) that can be manufactured separately using specialized processes, then bonded together. This modular approach allows each layer to be optimized independently while simplifying the overall manufacturing workflow.
Solution Approach 2:
The patent performs preliminary processing of each wafer layer before bonding, including surface preparation, pattern formation, and material deposition. By completing critical operations beforehand, the actual bonding process becomes simpler and more reliable, reducing overall manufacturing complexity despite the multi-layer structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the stack density of optical and electronic components and increases signal transfer speed by reducing parasitic effects, enabling more efficient on-chip optical signal processing.
Implementation Method 1
one of the electrically insulating layers is in direct contact with one of the further electrically insulating layers, whereby the electrically insulating layers form a pair of directly bonded layers
Implementation Method 2
The optical waveguide layer comprises at least one optical waveguide structure
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device comprises a semiconductor substrate (S) and a first metallization stack (MS1) arranged on the substrate (S). The substrate (S) comprises and/or carries a plurality of electronic circuit elements (CE). The first metallization stack (MS1) comprises electrically insulating layers (IL) and at least one metallization layer (ML). The semiconductor device further comprises a second metallization stack (MS2) arranged on the first metallization stack (MS2) and comprising further electrically insulating layers (ILF) and an optical waveguide layer (WL). The optical waveguide layer (WL) comprises at least one optical waveguide (WS1, WS2) structure. Furthermore, one of the electrically insulating layers (IL) is in direct contact with one of the further electrically insulating layers (ILF).