Semiconductor Device Dual Sealing Layer Thermal Management

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Solution Overview

Problem

Conventional semiconductor packages with exposed heat sinks face issues of adhesion strength due to thermal expansion mismatches, leading to poor thermal resistance and wire sweep problems, limiting bonding wire arrangement and causing electrical shorts.

Innovation Solution

A semiconductor device with a dual sealing layer structure, where a lower viscosity first sealing layer is used to prevent wire sweep and a higher thermal conductivity second sealing layer is applied above the heat sink to enhance thermal dissipation, ensuring low thermal resistance and high density without electrical shorts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a heat sink is sealed within the package using a sealing material, then adhesion strength is improved, but thermal resistance deteriorates due to high viscosity and large wire sweep

Engineering Contradiction:
Improveadhesion strengthVSAvoidthermal resistance
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The sealing structure is divided into two separate sealing layers: a first sealing layer for providing adhesion and structural support, and a second sealing layer specifically for thermal management. This segmentation allows each layer to be optimized for its specific function without compromise.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the sealing structure are assigned different material properties: the first sealing layer uses a material optimized for adhesion strength, while the second sealing layer uses a material with high thermal conductivity specifically for heat dissipation from the heat sink.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If a spacer is formed on the front surface of the semiconductor chip, then heat sink mounting is enabled, but bonding wire arrangement freedom is limited

Engineering Contradiction:
Improveheat sink mountingVSAvoidbonding wire arrangement freedom
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The bonding wire routing is moved from the front surface plane to the side dimension by routing wires along the vertical profile between bonding pads and bonding terminals, eliminating the need for horizontal wire routing over the chip surface and thus removing the constraint imposed by the spacer.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The dual sealing layer structure achieves excellent thermal resistance, allows for flexible bonding wire arrangement, and prevents wire sweep, thereby improving heat dissipation and manufacturing efficiency.

Implementation Method 1

a second sealing layer formed above the first sealing layer and having a higher thermal conductivity than a thermal conductivity of the first sealing layer

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

a heat sink 18 mounted above the first sealing layer by an adhesive

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS9412685B2Semiconductor device and method of manufacturing the same
Publication Date: 2016.08.09 AMKOR TECH JAPAN INC
  • US9412685B2 patent drawing
  • US9412685B2 patent drawing
  • US9412685B2 patent drawing

AI summary

A semiconductor device having a substrate including a plurality of external terminals on a rear surface and a plurality of bonding terminals electrically connected to the plurality of external terminals on a front surface, a semiconductor chip mounted on the front surface of the substrate, a surface of the chip including a plurality of bonding pads, a plurality of bonding wires connecting between the plurality of bonding pads or between the plurality of bonding terminals and the plurality of bonding wires respectively, a first sealing layer sealing the front surface of the substrate, the plurality of bonding wires and the semiconductor chip, and a second sealing layer comprised of the same material as the first sealing, the second sealing layer being formed above the first sealing layer.