Semiconductor Device Dual-Substrate Hybrid Bonding

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Solution Overview

Problem

Current semiconductor devices face challenges in miniaturization, low power consumption, and high performance due to limitations in memory cell arrangement and driving circuit integration.

Innovation Solution

The semiconductor device incorporates a dual-substrate structure with vertically arranged word lines and bit lines, and memory cells positioned between them, with driving circuits in separate substrates connected via hybrid bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If memory cells are arranged in a conventional planar configuration with driving circuits integrated on the same substrate, then the device structure is simple, but the cell region area is large and miniaturization is limited

Engineering Contradiction:
Improvecell region areaVSAvoiddevice structure
Core Design Contradiction:
Area of moving objectVSDevice complexity

Solution Approach 1:

The patent transitions from a conventional planar (2D) arrangement to a three-dimensional stacked configuration where memory cells are arranged vertically across multiple substrates. Word lines extend in a first direction, bit lines in a second direction, creating a 3D cross-point architecture that dramatically reduces the footprint area while maintaining memory capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The device is divided into multiple separate substrates (first substrate, second substrate, third substrate) that are stacked vertically. Each substrate contains specific components: the first substrate has driving circuits and portions of word/bit lines, the second substrate contains memory cells, and the third substrate has additional driving circuits. This segmentation allows independent optimization of each layer and reduces interconnections within a single substrate.

Inventive Principle:
Principle #1Segmentation

2Use of energy by moving object

If more memory cells are integrated on a single substrate with all driving circuits, then device complexity is low, but power consumption increases and performance is limited

Engineering Contradiction:
Improvepower consumptionVSAvoiddriving circuit integration
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

Driving circuits are segmented and distributed across multiple substrates rather than being集中 on a single substrate. The first driving circuits are on the first substrate, second driving circuits on the third substrate, allowing for better power management, heat dissipation, and reduced interference between circuit components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Bonding pads and interconnection structures serve as intermediaries between the driving circuits on different substrates and the memory cells on the second substrate. These intermediary elements enable efficient signal and power transmission across the stacked architecture while minimizing power loss and interference.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the cell region area, increases overlapped portions between word and bit lines, and allows for a more compact semiconductor device design while maintaining performance.

Implementation Method 1

coupling the first substrate structure and the second substrate structure by hybrid bonding

Methodology Applied
Scientific EffectHybrid bonding: Welding

Data Source

PatentUS20250061931A1Semiconductor device
Publication Date: 2025.02.20 SK HYNIX INC
  • US20250061931A1 patent drawing
  • US20250061931A1 patent drawing
  • US20250061931A1 patent drawing

AI summary

A semiconductor device may include: a first substrate structure including: a first substrate; a first word line, a first bit line, a second bit line, a second word line, a third word line, a third bit line, a fourth bit line, and a fourth word line that are sequentially arranged over the first substrate in a vertical direction; and first, second, third, and fourth memory cells, the first memory cell being disposed between the first word line and the first bit line, the second memory cell being disposed between the second word line and the second bit line, the third memory cell being disposed between the third word line and the third bit line, and the fourth memory cell being disposed between the fourth word line and the fourth bit line; and a second substrate structure disposed over the first substrate structure and including a second substrate.