Semiconductor Device Dummy Fin Isolation Structure
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Solution Overview
Problem
In semiconductor manufacturing, existing methods face challenges in achieving high chip density and preventing interlayer dielectric layer loss during the formation of isolation structures between metal gates, particularly when etching down to shallow trench isolation regions.
Innovation Solution
The method involves forming a semiconductor structure with a dummy fin between two fins on a substrate, etching away a portion of the metal gate overlapped with the dummy fin to create an opening, and depositing an insulating material to form an isolation structure, which separates the metal gates without the need for additional etching processes, thereby reducing ILD layer loss and facilitating easier shrinkage of the isolation structure width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional etching processes are used to form isolation structures between metal gates, then the isolation structure can be formed, but ILD layer loss occurs and manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming a dummy fin structure between the first and second fins before forming the isolation structure. This dummy fin serves as a pre-positioned template that defines the isolation structure width, eliminating the need for additional etching processes to achieve precise width control while preventing ILD layer loss.
Solution Approach 2:
The dummy fin acts as an intermediary element between the fins and the isolation structure. It provides a physical reference structure that mediates the formation process, allowing the isolation structure to be formed with precise width control without requiring complex etching sequences that would cause ILD layer loss.
2Productivity
If conventional methods are used to form isolation structures, then metal gates can be separated, but the process complexity increases and chip density is reduced
Solution Approach 1:
The dummy fin is formed in advance as part of the fin formation process, integrating the isolation structure definition into the existing manufacturing flow. This eliminates the need for separate etching processes, reducing manufacturing complexity while enabling tighter spacing between metal gates, thereby increasing chip density.
Solution Approach 2:
The patent merges the isolation structure formation with the fin formation process by using the dummy fin as a common element. The dummy fin serves dual purposes: as a structural element during fin formation and as a width-defining template for the isolation structure, combining multiple functions into a single integrated process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents ILD layer loss and allows for more precise control of isolation structure width, enhancing chip density and simplifying the process of connecting epitaxial source/drain regions with reduced risk of damage.
Implementation Method 1
etching away a portion of the metal gate overlapped with the dummy fin to cut off the metal gate
Implementation Method 2
depositing an insulating material to form an isolation structure
Data Source
AI summary
A semiconductor device includes a substrate, a first fin, a second fin, a dummy fin, a first metal gate, a second metal gate, and an isolation structure. The first, the second and the dummy fins are on the substrate, and the dummy fin is disposed between the first fin and the second fin. The first metal gate and the second metal gate are over the first fin and the second fin, respectively. The isolation structure is on the dummy fin, and the dummy fin and the isolation structure separate the first metal gate and the second metal gate.