Semiconductor Device Dummy Gate Leakage Suppression

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Solution Overview

Problem

In semiconductor devices, the variation in gate length due to differences in pattern density during exposure can lead to increased leakage current, particularly when dummy gate electrodes are used to improve pattern density uniformity.

Innovation Solution

A semiconductor device design where the concentration of carriers under dummy gate electrodes is lower than in the main gate electrode area, creating a depletion layer that suppresses the electric field and reduces junction leakage current, achieved through specific impurity concentrations and layer formations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If dummy gate electrodes are provided to improve pattern density uniformity, then manufacturing precision of gate electrode is improved, but leakage current increases

Engineering Contradiction:
Improvegate electrode pattern uniformityVSAvoidleakage current
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by creating a depletion layer with lower carrier concentration specifically in the region under the dummy gate electrode. This localized modification of electrical properties allows the dummy gate electrode to maintain pattern density uniformity while the depletion layer suppresses leakage current by reducing the concentration of majority carriers in the semiconductor substrate beneath the dummy gate structure.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If dummy gate electrodes are provided to improve pattern density uniformity, then gate length consistency is improved, but junction leakage current increases

Engineering Contradiction:
Improvegate length consistencyVSAvoidjunction leakage current
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent changes the physical parameter of carrier concentration in the semiconductor substrate under the dummy gate electrode. By creating a region with lower majority carrier concentration (depletion layer), the patent modifies the electrical characteristics to suppress leakage current while maintaining the dummy gate electrode's function of improving gate length consistency through pattern density uniformity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively reduces junction leakage current by suppressing the electric field under the dummy gate electrodes, improving the uniformity and accuracy of gate electrode processing while minimizing the impact of pattern density variations.

Implementation Method 1

the concentration of carrier of a first carrier type in the semiconductor substrate under the dummy gate electrode and alongside the second semiconductor area is lower than a concentration of majority carrier in the first semiconductor area

Methodology Applied
Scientific EffectDepletion layer:

Data Source

PatentUS11101358B2Semiconductor device and manufacturing method thereof
Publication Date: 2021.08.24 UNITED SEMICON JAPAN CO LTD
  • US11101358B2 patent drawing
  • US11101358B2 patent drawing
  • US11101358B2 patent drawing

AI summary

A semiconductor device includes a semiconductor substrate, a first semiconductor area of a first conductive type disposed in a surface layer portion of the semiconductor substrate, a gate electrode disposed over the first semiconductor area and extending in a first direction, a dummy gate electrode disposed over the semiconductor substrate away from the gate electrode and extending in the first direction, a second semiconductor area of a second conductive type disposed, in the surface layer portion of the semiconductor substrate, between the gate electrode and the dummy gate electrode, and an interconnect connected to the second semiconductor area, wherein a concentration of carrier of a first carrier type in the semiconductor substrate under the dummy gate electrode and alongside the second semiconductor area is lower than a concentration of majority carrier in the first semiconductor area, the first carrier type being a same carrier type as the majority carrier.