Semiconductor Structure Removing Dummy Gates for Power Reduction
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Solution Overview
Problem
Conventional semiconductor structures with dummy gate structures increase power consumption and circuit layout dimensions due to unnecessary gate structures between source and drain structures, limiting design flexibility and transistor performance.
Innovation Solution
A semiconductor structure without dummy gate structures, featuring vertically stacked transistors with gate structures only in the upper or lower transistors, and using conductive vias to connect source and drain structures, reducing the number of contact plugs and simplifying wire routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy gate structures are included between source and drain structures, then transistor fabrication is simplified, but power consumption increases and circuit layout dimensions increase
Solution Approach 1:
The patent removes dummy gate structures from the transistor design, extracting only the necessary functional elements. By eliminating non-functional gate structures between source and drain, the invention reduces power consumption while maintaining fabrication simplicity through selective gate formation in only the upper or lower transistors of vertically stacked configurations.
Solution Approach 2:
The patent transitions to vertically stacked transistor configurations, moving from planar to three-dimensional architecture. This dimensional change allows gates to be formed only in upper or lower transistors, eliminating the need for dummy gates in intermediate positions, thereby reducing power consumption without compromising manufacturability.
2Ease of manufacture
If dummy gate structures are included between source and drain structures, then transistor fabrication is simplified, but circuit layout dimensions increase
Solution Approach 1:
The patent extracts and removes dummy gate structures from the circuit layout, retaining only essential functional gates. This elimination of non-functional elements reduces the overall circuit footprint while maintaining fabrication simplicity through streamlined gate formation processes.
Solution Approach 2:
By adopting vertically stacked transistor architectures, the patent utilizes the third dimension to accommodate transistor structures, thereby reducing the planar footprint. Gates are formed only in upper or lower transistors, eliminating space-consuming dummy gates and reducing overall circuit layout dimensions.
3Ease of manufacture
If conventional source and drain connections are used, then manufacturing process is straightforward, but the number of contact plugs increases and wire routing becomes complex
Solution Approach 1:
The patent merges source and drain structures into vertically stacked configurations, combining multiple transistor elements into a compact three-dimensional arrangement. This consolidation reduces the number of separate contact plugs required and simplifies wire routing by eliminating redundant connections associated with dummy gate structures.
Solution Approach 2:
The transition to vertically stacked architectures utilizes the third dimension to reduce planar complexity. By stacking transistors vertically, the invention reduces the number of contact plugs needed for interconnections and simplifies wire routing paths, thereby reducing device complexity while maintaining manufacturing feasibility.
Data Source
AI summary
A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.