Semiconductor Device Dummy Gate Conductive Layer Thickness

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Solution Overview

Problem

The increasing demand for high-performance semiconductor devices with high integration and multifunctionality poses challenges in achieving improved electrical characteristics and production yield, particularly in scaling down transistors while maintaining reduced size and varied operating voltages.

Innovation Solution

The semiconductor device design incorporates a substrate with distinct regions, including active regions, gate structures, and dummy gate structures, where the dummy gate conductive layer has a different thickness than the gate conductive layers, and the use of filler cells and dummy structures to optimize mask density, allowing for varied threshold voltages and improved manufacturing processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If transistors are scaled down to achieve high integration, then device size is reduced and integration density increases, but electrical characteristics and production yield deteriorate

Engineering Contradiction:
Improvetransistor sizeVSAvoidelectrical characteristics and production yield
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by forming gate conductive layers with different thicknesses in different regions. Specifically, a first gate conductive layer with a first thickness is formed in a first region, and a second gate conductive layer with a second thickness (different from the first) is formed in a second region. This allows different threshold voltages to be achieved in different transistor regions, thereby maintaining electrical characteristics during scaling.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If multiple threshold voltages are required for different circuit functions, then device functionality increases, but device complexity increases

Engineering Contradiction:
Improvevaried threshold voltagesVSAvoidgate structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the gate conductive layer into multiple distinct layers with different thicknesses. A first gate conductive layer is formed in a first region and a second gate conductive layer is formed in a second region, where the second layer has a different thickness than the first. This segmentation enables different threshold voltages to be achieved through simple thickness variation rather than using entirely different structures, thus reducing complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20230223391A1Semiconductor device
Publication Date: 2023.07.13 SAMSUNG ELECTRONICS CO LTD
  • US20230223391A1 patent drawing
  • US20230223391A1 patent drawing
  • US20230223391A1 patent drawing

AI summary

A semiconductor device includes a substrate having first to fourth regions, first to third active regions and a first dummy active region extending on the first to fourth regions, respectively, a first gate structure intersecting the first active region on the first region and including a first gate conductive layer, a second gate structure intersecting the second active region on the second region and including a second gate conductive layer, a third gate structure intersecting the third active region on the third region find including a third gate conductive layer, a first dummy gate structure intersecting the first dummy active region on the fourth region and including a first dummy gate conductive layer, and source/drain regions on the first to third active regions and on both sides of the first to third gate structures.