Semiconductor Device Dummy Conductive Layer CMP Planarization
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Solution Overview
Problem
In semiconductor device manufacturing, the challenge lies in maintaining equal heights between the cell array and peripheral circuit regions during processes like CMP, where forming direct contacts and bit lines in the cell array and gate electrode structures in the peripheral circuit region simultaneously can lead to planarization issues and damage to the gate electrode structure.
Innovation Solution
The solution involves forming a dummy conductive layer in the peripheral circuit region with the same material as the direct contact, which serves as a CMP stopping layer, preventing damage to the gate electrode structure and ensuring reliable electrical characteristics by reducing dishing phenomena during planarization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is performed to maintain equal heights between cell array region and peripheral circuit region, then planarization is achieved, but dishing phenomena occur and gate electrode structure may be damaged
Solution Approach 1:
A dummy conductive layer is formed in the peripheral circuit region before the CMP process to serve as a stopping layer. This preliminary action prevents the CMP process from removing the gate electrode structure by providing a protective interface that stops the polishing action at the appropriate depth, thereby preventing dishing phenomena and structural damage while maintaining height equality.
2Productivity
If direct contact and bit line formation process is performed simultaneously with gate electrode structure formation process, then manufacturing efficiency is improved, but planarization control becomes difficult
Solution Approach 1:
The dummy conductive layer is selectively formed only in the peripheral circuit region where planarization control is needed, while the cell array region undergoes normal direct contact and bit line formation. This local differentiation allows simultaneous processing in different regions with different requirements, maintaining manufacturing efficiency while achieving precise planarization control in the peripheral circuit region.
Data Source
AI summary
A semiconductor device including a direct contact and a bit line in a cell array region and a gate electrode structure in a peripheral circuit region, and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate including a cell array region including a first active region and a peripheral circuit region including a second active region, a first insulating layer on the substrate, the first insulating layer including contact holes exposing the first active region, a direct contact in the contact holes, wherein a direct contact is connected to the first active region, a bit line connected to the direct contact in the cell array region and extending in a first direction, and a gate insulating layer and a gate electrode structure, wherein a dummy conductive layer including substantially the same material as the direct contact is in the peripheral circuit region.