Semiconductor Device Dummy Opening Metal Layer Bonding
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Solution Overview
Problem
Advanced packaging techniques in the electronics industry face challenges in achieving strong and reliable chip-to-chip bonding due to surface oxidation of metal bonding materials, which degrades bonding strength and quality, especially in wafer-level chip scale packaging and hermetic packaging methods.
Innovation Solution
A manufacturing method involving dielectric-to-dielectric bonding or copper-to-copper bonding of semiconductor wafers, with the introduction of through openings and corresponding metal layers to form dummy openings and functional vias, which enhance bonding strength by reducing voids and delamination risks and improve handling during the dicing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If metal bonding materials are used for chip-to-chip bonding, then bonding strength can be achieved, but surface oxidation degrades bonding quality and strength
Solution Approach 1:
A dielectric layer is introduced as an intermediary between metal bonding materials on different chips. This dielectric layer prevents direct metal-to-metal contact that would cause oxidation issues, while still enabling bonding through its own adhesive properties. The dielectric acts as a protective mediator that maintains bonding strength without the degradation caused by surface oxidation.
Solution Approach 2:
The patent creates an oxidation-resistant environment by covering metal bonding surfaces with a dielectric material that prevents oxygen access. This effectively creates an inert protective environment around the metal bonding interfaces, preventing oxidation during the time delay between bonding material deposition and actual bonding operation.
2Ease of manufacture
If time delay occurs between deposition of bonding material and actual bonding, then processing flexibility is improved, but metal surfaces oxidize during delay
Solution Approach 1:
The bonding metal layers are deposited and patterned in advance on separate chips before the actual bonding operation. This preliminary preparation allows for flexible scheduling and processing, while the subsequent bonding step quickly joins the pre-prepared surfaces, minimizing the time they remain exposed to oxidation.
Solution Approach 2:
The dielectric layer serves as a protective intermediary that can be applied to metal bonding surfaces during the time delay period, preventing oxidation while allowing processing flexibility. This mediator enables the time delay necessary for manufacturing flexibility without sacrificing bonding strength.
3Productivity
If wafer-level chip scale packaging is used to reduce package size, then integration level increases, but bonding surfaces are more susceptible to oxidation and delamination
Solution Approach 1:
In wafer-level chip scale packaging where multiple chips are bonded directly together, dielectric layers are introduced at the bonding interfaces as protective intermediaries. This prevents oxidation of the metal bonding surfaces and reduces delamination risk, enabling high integration levels while maintaining bonding surface quality and reliability.
Solution Approach 2:
The bonding structure uses composite material layers combining metal bonding materials with dielectric protective layers. This composite approach leverages the adhesive properties of metals while incorporating the oxidation resistance and delamination prevention properties of dielectrics, suitable for advanced packaging techniques.
4Device complexity
If direct chip-to-chip bonding is performed without protective structures, then manufacturing process is simplified, but edges of chips are susceptible to cracking and chipping
Solution Approach 1:
Protective structures such as dielectric layers and reinforcement features are introduced beforehand at chip edges and bonding interfaces. These protective elements act as cushions against mechanical stress during handling and dicing processes, preventing cracking and chipping while maintaining relative manufacturing process simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly improves bonding strength and reliability of semiconductor devices by reducing delamination and cracking risks, enhancing the quality of wafer-level packaging and hermetic sealing, and maintaining the integrity of the semiconductor device during handling and environmental exposure.
Implementation Method 1
the bonding surfaces are prone to oxidation after they have been formed and patterned and the presence of a surface oxide limits metal to metal diffusion such as needed to form a strong metal bond
Implementation Method 2
The first integrated circuit includes a semiconductor substrate and a dielectric layer disposed on a top surface of the semiconductor substrate
Data Source
AI summary
A semiconductor device includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a semiconductor substrate and a dielectric layer disposed on a top surface of the semiconductor substrate. The second integrated circuit is disposed on the dielectric layer of the first integrated circuit and includes a dummy opening extending through the second integrated circuit and having a metal layer covering the inner walls of the dummy opening and in contact with the dielectric layer, wherein the metal layer is electrically grounded or electrically floating.