Semiconductor Package Dummy Pattern Relocation for Bonding

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Solution Overview

Problem

Existing semiconductor packaging technologies face challenges in achieving reliable vertical stacking and bonding of semiconductor chips due to the placement of dummy patterns on the substrate surface, leading to low bonding efficiency and potential bonding failures.

Innovation Solution

The semiconductor device design features a dummy pattern positioned on the protruding portion of the insulating layer outside the substrate, avoiding placement on the substrate surface, which enhances the efficiency of vertical stacking and bonding between semiconductor chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If dummy patterns are placed on the substrate surface, then the insulating layer structure is simplified, but bonding efficiency decreases and bonding failures occur

Engineering Contradiction:
Improveinsulating layer structure simplicityVSAvoidbonding reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The dummy pattern is relocated from the substrate surface (2D plane) to the protruding portion of the insulating layer (3D space), utilizing the vertical dimension to resolve the conflict between manufacturing simplicity and bonding reliability. This spatial repositioning allows the dummy pattern to maintain its structural function while eliminating interference with bonding operations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The dummy pattern is extracted from the substrate surface and placed on the insulating layer protrusion, separating the dummy pattern function from the bonding interface. This extraction eliminates the harmful interaction between dummy patterns and bonding processes while preserving the insulating layer's structural simplicity.

Inventive Principle:
Principle #2Taking out (Extraction)

2Ease of manufacture

If dummy patterns are placed on the substrate surface, then manufacturing process is simpler, but bonding efficiency becomes low

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidbonding efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

By moving the dummy pattern to the protruding portion of the insulating layer, the invention utilizes vertical space to separate the dummy pattern from the bonding interface, maintaining manufacturing simplicity while significantly improving bonding efficiency by eliminating process interruptions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The dummy pattern is extracted from the bonding area and positioned on the insulating layer protrusion, allowing bonding operations to proceed without interruption while maintaining the simplified manufacturing approach of using dummy patterns for structural support.

Inventive Principle:
Principle #2Taking out (Extraction)

3Strength

If dummy patterns are placed on the substrate surface, then structural support is provided, but bonding failures occur

Engineering Contradiction:
Improvestructural supportVSAvoidbonding reliability
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The dummy pattern is repositioned to the protruding portion of the insulating layer, utilizing the vertical dimension to maintain structural support function while removing the pattern from the bonding interface plane, thereby preventing bonding failures caused by pattern interference.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The dummy pattern is extracted from the substrate surface and placed on the insulating layer protrusion, separating the structural support function from the bonding interface. This allows the dummy pattern to continue providing structural reinforcement while eliminating the cause of bonding failures.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20230089399A1Semiconductor device and semiconductor package including the same
Publication Date: 2023.03.23 SAMSUNG ELECTRONICS CO LTD
  • US20230089399A1 patent drawing
  • US20230089399A1 patent drawing
  • US20230089399A1 patent drawing

AI summary

A semiconductor device includes a substrate, an insulating layer on a bottom surface of the substrate, a portion of a top surface of the insulating layer that faces the substrate being exposed outside a side surface of the substrate, a through via penetrating the substrate, an interconnection structure in the insulating layer, and a dummy pattern on the portion of the top surface of the insulating layer that is exposed by the substrate.