Semiconductor Dummy Pattern Design for CMP Planarity

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Solution Overview

Problem

The CMP process used in semiconductor manufacturing often results in dishing and erosion phenomena, leading to uneven surface planarity and difficulties in forming small wiring patterns due to variations in wiring density, which conventional dummy pattern design methods fail to adequately address.

Innovation Solution

A method for designing a dummy pattern that involves setting an overall dummy section on the chip region, dividing it into a mesh section to form rectangular dummy patterns, and performing specific processes to remove and synthesize these patterns to achieve uniform density and disposition, thereby inhibiting dishing and erosion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the CMP process is used to planarize the semiconductor substrate surface, then surface planarity is improved, but dishing and erosion phenomena occur leading to non-uniform surface depth

Engineering Contradiction:

Improvesurface planarityVSAvoiddishing and erosion phenomena

Core Design Contradiction:

Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

Dummy patterns are formed in advance in vacant sections of the chip region before the CMP process. These dummy patterns pre-compensate for areas that would otherwise be over-polished, ensuring uniform material removal depth during CMP and preventing dishing and erosion phenomena.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Dummy patterns are selectively formed only in vacant sections where wiring density is low, while leaving device graphics data sections unchanged. This local application of dummy patterns creates uniform wiring density distribution specifically in areas prone to dishing and erosion, without affecting functional device regions.

Inventive Principle:

Principle #3Local quality

2Reliability

If wiring density is non-uniform on the substrate surface, then device functionality is maintained, but dishing and erosion phenomena occur during CMP

Engineering Contradiction:

Improvedevice functionalityVSAvoiddishing and erosion phenomena

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

Inventive Principle:

Principle #3Local quality

3Quantity of substance

If conventional dummy pattern design methods are used, then some dummy patterns are formed, but uniform density and optimal disposition are not achieved

Engineering Contradiction:

Improvedummy pattern coverageVSAvoiddummy pattern density uniformity

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The system calculates wiring density distribution across the chip region, identifies vacant sections with non-uniform density, and strategically places dummy patterns in those specific areas. This feedback-driven approach ensures dummy patterns are formed with optimal density and disposition to achieve uniform overall wiring density and prevent CMP defects.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The chip region is divided into device graphics data sections and vacant sections. Dummy patterns are independently designed and formed only in vacant sections, allowing precise control over dummy pattern density and disposition without interfering with functional device regions.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method ensures uniform dummy pattern density and disposition, preventing dishing and erosion, and enhancing surface planarity, allowing for improved formation of small wiring patterns and increased depth of focus in lithography.

Implementation Method 1

the surface of a semiconductor substrate is planarized using a chemical mechanical polishing (CMP) process

Methodology Applied

Scientific EffectChemical mechanical polishing:

Implementation Method 2

If a pattern (hereafter referred to as a 'dummy pattern') that is formed by the material with the same properties as those of the wiring material is formed in a region free from wiring on a surface of a semiconductor substrate, the wiring density on the surface of the semiconductor substrate can be made uniform

Methodology Applied

Scientific EffectDensity uniformization:

Data Source

PatentUS9570378B2Semiconductor device including dummy pattern

Publication Date: 2017.02.14 LONGITUDE LICENSING LTD

AI summary

A semiconductor device includes a substrate including a circuit region, a dummy region, and a dummy clearance section surrounding the circuit region, and a plurality of dummy patterns formed in the dummy region, the plurality of dummy patterns comprising a first dummy pattern and a second dummy pattern, a distance between the first dummy pattern and the circuit region being less than a distance between the second dummy pattern and the circuit region, and a dummy pattern being absent between the first dummy pattern and the circuit region. The first dummy pattern includes an area which is greater than an area of the second dummy pattern.