Dummy Patterns for Semiconductor Lithography Process Margin

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Solution Overview

Problem

Low-density pattern areas in semiconductor manufacturing exhibit reduced process margin and increased etch bias during photolithography, leading to deteriorated uniformity and depth of focus issues, which conventional assist features fail to adequately address.

Innovation Solution

Forming dummy patterns of the same size as the main pattern over inactive areas adjacent to active areas in a low-density pattern area, spaced according to a design rule, to increase pattern density and reduce etch bias.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a photolithography process is used to form patterns in low-density pattern areas, then the main pattern can be formed, but the process margin is reduced and etch bias increases

Engineering Contradiction:
Improveprocess marginVSAvoiduniformity of critical regions
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

Dummy patterns are formed in advance in the low-density pattern area before the main photolithography process. These dummy patterns pre-establish the required pattern density and distribution, which then serves as a reference for the subsequent light exposure process, ensuring uniform etch bias and improving process margin.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy patterns are selectively placed only in the low-density pattern areas where the problem occurs, rather than uniformly across the entire wafer. This localized approach addresses the specific uniformity issue in low-density regions without affecting high-density areas, optimizing the overall process margin.

Inventive Principle:
Principle #3Local quality

2Reliability

If assist features are used on the exposure mask to improve uniformity in low-density areas, then the depth of focus margin is slightly improved, but etch bias control remains insufficient

Engineering Contradiction:
Improveuniformity margin of critical regionsVSAvoidetch bias control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

Instead of using assist features that only slightly improve uniformity, the invention forms actual dummy patterns in advance that fully establish the required pattern density. This preliminary action creates a realistic reference for the etching process, effectively controlling etch bias rather than just providing marginal improvement.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy patterns are formed as actual pattern copies with the same dimensions and spacing characteristics as the main patterns. These copied patterns provide an authentic reference for the etching process, enabling proper etch bias control that mimics the actual pattern conditions rather than using simplified assist features.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS8105757B2Method of making a semiconductor device
Publication Date: 2012.01.31 SK HYNIX INC
  • US8105757B2 patent drawing
  • US8105757B2 patent drawing
  • US8105757B2 patent drawing

AI summary

Disclosed is a method of making a semiconductor device in which a main pattern is formed through a photolithography process over a low-density pattern area having a relatively small number of patterns to be formed in certain areas as compared to the other areas. According to the method at least one or more dummy patterns are formed over inactive areas, adjacent to active areas, where the main pattern is formed, and are spaced a predetermined distance from the sides of the main pattern. This method can improve the process margin and improve the uniformity of critical regions of patterns to thus improve the yield of a semiconductor device by making a low-density pattern area with the same pattern density as high-density or intermediate-density pattern areas by forming dummy patterns, which do not affect the semiconductor device, on the sides of a main pattern of the low-density pattern area according to a design rule.