Semiconductor Dummy Patterns for Power Noise Protection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The reduction in transistor gate length in semiconductor memory apparatuses leads to direct coupling with power supply or ground voltage, causing potential breakdown of the gate oxide and compromising the reliability of semiconductor memory apparatuses due to power noise.

Innovation Solution

Incorporating dummy pattern blocks around the main pattern blocks, which include protection elements such as resistors and diodes, to form additional power transmission paths and mitigate noise from power supply or ground voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the gate length of a transistor is shortened to accommodate higher integration and high-speed operation, then the operation speed and integration capability are improved, but the gate oxide may be broken by power noise and reliability is degraded

Engineering Contradiction:
Improveoperation speedVSAvoidgate oxide reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent introduces dummy patterns as intermediary elements between the main transistor patterns and power supply/ground lines. These dummy patterns act as mediators that intercept and dissipate power noise before it reaches the main patterns, thereby protecting the gate oxide while maintaining the shortened gate length for high-speed operation

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dummy patterns are placed in advance around the main patterns to provide protective cushioning against power noise. This prior protection structure absorbs and redirects noise energy before it can damage the gate oxide of the main transistors, enabling reliable high-speed operation

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Productivity

If the gate of the transistor is directly coupled to power supply voltage VDD or ground voltage VSS to accommodate shorter gate lengths, then the transistor performance is improved, but power noise directly affects the gate oxide and reliability is compromised

Engineering Contradiction:
Improvetransistor performanceVSAvoidpower noise effect
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

Dummy patterns are introduced as intermediary elements between the main transistor patterns and power supply/ground lines. These dummy patterns act as mediators that intercept and dissipate power noise before it reaches the main patterns, thereby protecting the gate oxide while maintaining the shortened gate length for high-speed operation

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The harmful power noise is extracted and redirected away from the main transistor patterns through the dummy patterns. The dummy patterns serve as separate entities that capture and channel noise energy, preventing it from affecting the main patterns while allowing direct power coupling for performance

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If dummy pattern blocks are formed around the main pattern block to protect from power noise, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveoverall reliabilityVSAvoidpattern structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The semiconductor device is segmented into distinct functional blocks: main pattern blocks for performance-critical transistors and dummy pattern blocks for protection. This segmentation allows the protective function to be added modularly around the main patterns without fundamentally redesigning the core transistor structure, managing complexity through functional separation

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9171835B2Semiconductor apparatus including dummy patterns
Publication Date: 2015.10.27 SK HYNIX INC
  • US9171835B2 patent drawing
  • US9171835B2 patent drawing
  • US9171835B2 patent drawing

AI summary

A semiconductor apparatus and system including a semiconductor apparatus may include: a main pattern block having a plurality of main patterns formed to be coupled to a power source and one or more dummy pattern blocks formed around the main pattern block. Any one of the one or more dummy pattern blocks may include a protection part formed to protect the main pattern block.