Semiconductor Device Dummy Pillar Lithography Correction
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Solution Overview
Problem
Vertical transistors with reduced cross-sectional area of semiconductor pillars face limitations in current driving capability, leading to variations in transistor characteristics due to the optical proximity effect during lithography, especially when combined with gate-lifting pillars of different sizes, resulting in inconsistent performance in parallel connection transistors.
Innovation Solution
The implementation of a semiconductor device design that includes a second dummy pillar with a smaller two-dimensional pattern between transistor pillars and a first dummy pillar with a larger pattern, arranged to correct the optical proximity effect and maintain uniformity in transistor pillar dimensions, ensuring stable characteristics in parallel connection transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a gate-lifting pillar with a two-dimensional pattern different from semiconductor pillars is used to supply electric power, then the gate electrode can be powered, but the optical proximity effect varies during lithography causing dimensional variations in adjacent semiconductor pillars
Solution Approach 1:
A dummy semiconductor pillar is introduced as an intermediary structure between the gate-lifting pillar and the transistor pillars. This dummy pillar has the same two-dimensional pattern as the transistor pillars, serving as a buffer that prevents the optical proximity effect from the differently-sized gate-lifting pillar from directly affecting the transistor pillars, thereby maintaining dimensional uniformity while allowing the gate-lifting pillar to perform its power supply function
2Reliability
If the cross-sectional area of semiconductor pillars is reduced to achieve full depletion, then channel full depletion is achieved with good S value, but current driving capability decreases
Solution Approach 1:
Multiple semiconductor pillars are arranged in parallel within the active region, each pillar maintaining a small cross-sectional area to achieve full channel depletion and good S value characteristics. The parallel connection of multiple pillars collectively provides sufficient current driving capability, thus resolving the contradiction between individual pillar size and overall device performance
Data Source
AI summary
A semiconductor device has an active region defined by a device isolation region arranged on a surface of a semiconductor substrate, a plurality of transistor pillars arranged along a first direction within the active region, and a first dummy pillar disposed in the device isolation region. The first dummy pillar is arranged on a line extending along the first direction from the transistor pillars. The semiconductor device also has a second dummy pillar disposed between the transistor pillars and the first dummy pillar, a gate electrode continuously extending so as to surround each of side surfaces of the transistor pillars, a first power supply gate electrode surrounding a side surface of the first dummy pillar, and a second power supply gate electrode surrounding a side surface of the second dummy pillar. The second power supply gate electrode is connected to the gate electrode and the first power supply gate electrode.