Semiconductor Internal Circuit Refresh via Dummy Read Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices face deterioration due to long-term deactivation of internal circuits, leading to distortion of duty ratios in internal signals, which affects the performance of PMOS and NMOS transistors.
Innovation Solution
The semiconductor device incorporates a memory core circuit and data control circuit that generate core data from bank data or dummy column addresses, and switching signals based on read operations, preventing internal circuit deterioration by toggling logic levels during inactive periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If internal circuits are deactivated for long periods, then power consumption is reduced, but transistor deterioration occurs due to fixed logic levels
Solution Approach 1:
The patent applies periodic action by implementing a dummy read operation that periodically toggles logic levels in internal circuits during deactivated periods. The dummy read operation is executed at predetermined intervals to refresh transistor characteristics without requiring full active operation, thus maintaining reliability while keeping the circuit mostly deactivated for power savings.
Solution Approach 2:
The patent uses preliminary action by performing dummy read operations before actual read operations to refresh transistor characteristics. This preliminary refreshing prevents deterioration that would occur during extended deactivation, ensuring that when the circuit is needed, the transistors are in optimal condition.
2Loss of energy
If internal circuits remain deactivated, then power savings are achieved, but duty ratio distortion occurs in internal signals
Solution Approach 1:
The dummy read operation periodically toggles clock signals and internal control signals at predetermined intervals during deactivated periods. This periodic toggling prevents duty ratio distortion by ensuring that signal paths remain active and balanced, maintaining signal integrity while the circuit remains mostly deactivated for power savings.
Solution Approach 2:
The patent maintains continuity of useful action by executing dummy read operations that keep critical signal paths active during deactivated periods. This continuous refreshing of signal paths prevents duty ratio distortion without requiring the entire circuit to remain fully operational, thus achieving power savings while maintaining signal stability.
3Reliability
If dummy read operations are performed periodically, then transistor deterioration is prevented, but additional power consumption occurs
Solution Approach 1:
The dummy read operation is executed at predetermined intervals rather than continuously, striking a balance between refreshing transistor characteristics and minimizing additional power consumption. The periodic execution ensures transistor reliability is maintained while limiting the frequency of power-consuming refresh operations.
Solution Approach 2:
The patent applies partial action by performing only the minimal necessary dummy read operations required to refresh transistor characteristics, rather than executing complete read operations. This partial execution achieves the necessary transistor refreshing while consuming less additional power than full read operations would require.
Data Source
AI summary
A semiconductor device includes a memory core circuit configured to generate core data from bank data outputted by a bank or generate the core data from a dummy column address based on a read operation for the bank. The semiconductor device also includes a data control circuit configured to generate a switching signal from a bank active signal or a dummy bank address based on the read operation for the bank and and configured to control the output of the core data based on the switching signal.