Semiconductor Dummy Terminal Layout for COG Load Balancing
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Solution Overview
Problem
Existing COG-implementation methods for semiconductor devices face challenges in reducing fabrication costs and optimizing chip size due to the need for large areas on glass substrates, especially when incorporating dummy terminals for load balancing during pressure welding, which limits the integration of multiple circuits and additional functions.
Innovation Solution
A semiconductor device design featuring terminals arrayed in a first pattern near one end and dummy terminals in a different pattern at a different region, allowing for increased layout flexibility and reduced chip size by optimizing the placement and arrangement of dummy terminals to maintain load balance during pressure welding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy terminals are added for load balancing during pressure welding, then connecting strength and reliability are improved, but chip area and substrate area increase
Solution Approach 1:
The patent applies local quality by creating distinct terminal patterns in different regions: real terminals in a first pattern at a first location for electrical connection, and dummy terminals in a second pattern at a second location for load balancing. This spatial differentiation allows each region to serve its specific function optimally without compromising overall chip area.
Solution Approach 2:
The terminal array is segmented into functionally distinct groups: real terminals for signal/power transmission and dummy terminals for mechanical load balancing during pressure welding. This segmentation allows the dummy terminals to be strategically placed in regions that do not interfere with the electrical connection requirements of the real terminals, thereby maintaining reliability while controlling chip area.
2Reliability
If dummy terminals are added for load balancing, then pressure welding reliability is improved, but fabrication cost increases
Solution Approach 1:
By assigning dummy terminals to specific regions with different functional requirements, the patent ensures that load balancing is achieved without unnecessarily increasing the overall terminal count or complicating the fabrication process. The localized placement optimizes the balance between reliability and manufacturing simplicity.
3Ease of manufacture
If chip size is reduced to lower fabrication cost, then fabrication cost decreases, but layout freedom is limited
Solution Approach 1:
The patent segments the chip into functional regions with real terminals and dummy terminals placed in distinct patterns. This segmentation allows for optimized space utilization, enabling reduced chip size while preserving layout freedom for circuit design within the available area.
Solution Approach 2:
The patent utilizes spatial arrangement in multiple dimensions by creating different terminal patterns (first pattern and second pattern) at different locations. This dimensional approach to terminal placement maximizes the use of available chip area, providing layout freedom even in compact designs.
Data Source
AI summary
Keeping more space for circuit elements on a chip when dummy terminals for reinforcement are located on it for the purpose of load balancing for pressure welding. A semiconductor device 10 used for COG-implementation comprising an output terminals group 12f arrayed in a first pattern close to one end of a chip, and one or more dummy terminals 12d located close to the one end of the chip in a different region from a region where an output terminals group 12f is located and arrayed in a second pattern different from the first pattern. The second pattern has a shortened width. A power supply portion 14 is located longitudinally adjacent to an output terminals group 12f beside the dummy terminals 12d.