Semiconductor Device Dummy Trench Segmentation for Capacitance Control
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Solution Overview
Problem
Increasing the ratio of the dummy trench portion to the gate trench portion in semiconductor devices leads to decreased capacitance between the collector and gate (CCG) and increased capacitance between the collector and emitter (CCE), causing oscillation phenomena.
Innovation Solution
A semiconductor device design that includes a semiconductor substrate with gate trench and dummy trench portions, where the dummy trench portion has an upper dummy conductive portion and a lower gate conductive portion, connected to the gate conductive portion of the gate trench, to adjust the parasitic capacitance and prevent oscillation by maintaining a stable capacitance ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ratio of the dummy trench portion to the gate trench portion is increased, then the capacitance between the collector and gate (CCG) is decreased, but the capacitance between the collector and emitter (CCE) is increased causing oscillation phenomena
Solution Approach 1:
The dummy trench portion is segmented into two distinct conductive portions: an upper dummy conductive portion and a lower gate conductive portion. This segmentation allows each portion to serve different functions - the upper portion maintains emitter potential to reduce CCG, while the lower portion maintains gate potential to control CCE and prevent oscillation phenomena.
Solution Approach 2:
Different regions of the dummy trench portion are assigned different electrical potentials and functions. The upper dummy conductive portion has emitter potential for capacitance reduction, while the lower gate conductive portion has gate potential for oscillation control. This local differentiation resolves the contradiction by optimizing each region's contribution to the overall capacitance characteristics.
2Speed
If the ratio of the dummy trench portion is increased to reduce CCG, then switching speed is improved, but oscillation phenomenon occurs due to increased CCE
Solution Approach 1:
By dividing the dummy trench portion into upper and lower conductive portions with different potentials, the patent enables simultaneous optimization of switching speed (through reduced CCG from the upper portion) and oscillation stability (through controlled CCE from the lower portion).
Solution Approach 2:
The patent changes the electrical potential parameter of different regions within the dummy trench portion. The upper portion maintains emitter potential while the lower portion maintains gate potential, thereby changing the capacitance characteristics to achieve both fast switching and oscillation-free operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively adjusts parasitic gate capacitance, reducing the likelihood of oscillation phenomena while maintaining efficient carrier accumulation and reducing on-state voltage drop.
Implementation Method 1
When the ratio of the dummy trench portion, having the conductive portion which is an emitter potential, with respect to the gate trench portion, is increased, the capacitance between the collector and the gate (hereinafter, CCG) is decreased and the capacitance between the collector and the emitter (hereinafter, CCE) is increased.
Data Source
AI summary
A semiconductor device includes: a first conductivity-type semiconductor substrate; a second conductivity-type base region provided on a front surface side inside the semiconductor substrate, a gate trench portion provided inside the semiconductor substrate and penetrating the base region from a front surface of the semiconductor substrate, the gate trench portion having a gate conductive portion, and a dummy trench portion provided inside the semiconductor substrate and penetrating the base region from a front surface of the semiconductor substrate, the dummy trench portion including an upper dummy conductive portion having an emitter potential and a lower gate conductive portion positioned below the upper dummy conductive portion and having a gate potential, wherein the lower gate conductive portion of the dummy trench portion is connected to the gate conductive portion of the gate trench portion.