Semiconductor Device Dummy Via Density Optimization
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Solution Overview
Problem
The existing semiconductor device technologies face challenges in maintaining mechanical strength and reliability of multilayer wiring due to the use of low-k interlayer insulation films, which requires high-density dummy via arrangements to comply with design standards, leading to expanded file sizes of layout CAD data.
Innovation Solution
A semiconductor device with a substrate and multiple wiring layers, featuring high-density dummy via patterns near wirings and low-density patterns in distant regions, connected by interlayer insulation films, to balance design compliance and file size management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-density dummy via arrangement is used to comply with design standards, then mechanical strength and reliability are improved, but file size of layout CAD data increases
Solution Approach 1:
The patent applies local quality by differentiating dummy via density based on spatial location: high-density dummy via patterns are placed in regions close to wirings where mechanical support is critical, while low-density patterns are used in distant regions where support requirements are lower. This resolves the contradiction by optimizing mechanical strength locally without uniformly increasing file size across the entire layout.
2Reliability
If high-density dummy via arrangement is used to comply with design standards, then mechanical strength and reliability are improved, but data handling efficiency decreases
Solution Approach 1:
By implementing variable dummy via density based on proximity to wirings, the patent reduces the total quantity of dummy vias required while maintaining mechanical strength in critical regions. This decreases the overall data volume that needs to be processed, thereby improving data handling efficiency without compromising reliability.
3Reliability
If uniform high-density dummy via pattern is used throughout, then mechanical strength is improved, but manufacturing complexity increases
Solution Approach 1:
The patent simplifies manufacturing by implementing a rule-based approach where dummy via density is determined by the distance to nearby wirings. This creates a manageable two-tier pattern system (high-density near wirings, low-density in distant regions) that is easier to manufacture than complex non-uniform patterns, while still providing targeted mechanical support where needed.
Data Source
AI summary
A first dummy via pattern having high density is arranged in the vicinity of first and second wirings on a semiconductor device, and a second dummy via pattern having low density is arranged in a distant region from the first and second wirings, with reference to the first dummy via pattern. Accordingly, it is possible to suppress expansion of the file size of layout CAD data due to dummy vias, while complying with a design standard regulated for each semiconductor process, regardless of the presence or absence of vias which connect the first wirings to the second wirings.