Semiconductor Duty Cycle Calibration Overlap
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Solution Overview
Problem
In semiconductor apparatus with multiple memory chips connected via an interface chip, the calibration operation of duty adjustment circuits is inefficient, leading to increased training time and system overhead due to sequential execution across multiple chips.
Innovation Solution
The calibration operation of read duty adjustment circuits is collectively executed across all chips, with overlapping periods for interface chip and memory chip calibration, and the use of dedicated commands for simultaneous or separate execution modes to stabilize the duty cycle correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If calibration operation is performed sequentially on each chip, then the calibration process is simple to control, but the overall training time increases and system overhead increases
Solution Approach 1:
The patent merges the calibration operations of multiple chips into a single collective calibration process. The interface chip and multiple memory chips perform calibration simultaneously through coordinated command execution, where the interface chip issues calibration commands and receives calibration results from all chips in parallel, thereby reducing total training time while maintaining manageable control complexity
Solution Approach 2:
The patent implements continuous calibration action by having the interface chip and memory chips perform calibration operations in overlapping time periods. The calibration process is designed to proceed without idle waiting time, where chips that have completed their calibration can immediately assist in the calibration of other chips, ensuring continuous productive action throughout the calibration phase
2Loss of time
If calibration operation is performed collectively across all chips, then the training time is shortened, but the coordination complexity between interface chip and memory chips increases
Solution Approach 1:
The patent segments the collective calibration process into distinct phases: initialization phase where the interface chip sets up calibration parameters, execution phase where all chips perform calibration simultaneously, and completion phase where calibration results are collected. This segmentation reduces coordination complexity by breaking down the complex collective operation into manageable sequential steps with clear boundaries
Solution Approach 2:
The interface chip acts as an intermediary that coordinates the collective calibration process. It issues calibration commands to all memory chips, collects calibration results from them, and manages the timing and synchronization of the calibration operations. This intermediary role simplifies the coordination complexity by centralizing control functions in a single chip that manages the calibration of all other chips
Data Source
AI summary
According to one embodiment, there is provided a semiconductor apparatus including a first chip and a second chip. The first chip is electrically connected to a terminal to which a signal from a host device is input. The second chip is electrically connected to the first chip. The second chip has a first duty adjustment circuit. The first chip has a second duty adjustment circuit. The first duty adjustment circuit performs first calibration operation in a first period. The second duty adjustment circuit performs second calibration operation in a second period. The first period and the second period have an overlapping period.