Semiconductor Device Dynamic Erase Verification
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Solution Overview
Problem
The reliability of semiconductor devices is compromised due to erroneous determination of completely erased cells during the erase operation, caused by deteriorated electrical characteristics leading to increased current measurements above the sensing reference level.
Innovation Solution
An additional erase verification operation is performed with an increased sensing reference level when the normal erase verification fails, allowing for repeated erase operations and accurate detection of completely erased cells by changing the sensing reference level in the control circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed sensing reference level is used for erase verification, then the verification process is simple and fast, but electrical characteristic deterioration causes erroneous determination of erased cells
Solution Approach 1:
The sensing reference level is changed from a fixed value to a dynamic value that varies based on the erase verification results. When cells are erroneously determined as not erased, the reference level is adjusted (increased) for subsequent verification operations, allowing the system to adapt to electrical characteristic deterioration over time.
Solution Approach 2:
The system implements a feedback mechanism where the result of each erase verification operation is used to adjust the sensing reference level for the next verification. The control circuit monitors whether cells are erroneously determined and automatically modifies the reference level accordingly, creating a closed-loop control system that improves reliability.
2Measurement precision
If the sensing reference level is increased to correctly identify erased cells, then measurement accuracy improves, but the verification process becomes more complex
Solution Approach 1:
The sensing reference level parameter is dynamically changed based on verification results. Instead of using a single fixed threshold, the system adjusts this parameter (increases it) when electrical characteristic deterioration is detected, thereby maintaining measurement precision without requiring a completely different sensing mechanism.
3Reliability
If multiple erase verification operations are performed with adjusted reference levels, then reliability improves, but operation time increases
Solution Approach 1:
The system performs verification operations with adjusted reference levels only when necessary - specifically when cells are erroneously determined as not erased. This partial application of the time-consuming verification process balances reliability improvement with time efficiency, avoiding unnecessary repeated verifications.
Data Source
AI summary
A semiconductor device and an operating method thereof comprise peripheral circuits configured to apply an erase voltage to memory cells when performing an erase operation, and sense a voltage change of bit lines by an erase verification voltage applied to word lines of the memory cells when performing an erase verification operation to thereby detect cells which are not erased, and a control circuit configured to control the peripheral circuits by changing a sensing reference level for determining the voltage change of the bit lines when the cells which are not erased are detected when performing the erase verification operation, so that the erase verification operation is repeatedly performed.