Semiconductor ECC Area Dynamic Allocation
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Solution Overview
Problem
As semiconductor devices with reduced cell size and lower voltage face deteriorating soft error tolerance, existing error correction code (ECC) circuits require additional parity bits, leading to increased storage space and potential system errors, especially as the data area size grows.
Innovation Solution
The semiconductor device dynamically assigns a small ECC area to only some data areas at a time, performing ECC operations sequentially and storing parity data accordingly, allowing for reduced parity bit storage space and adaptive error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC operation is performed on all data areas simultaneously, then error correction coverage is maximized, but parity bit storage space increases significantly
Solution Approach 1:
The patent divides the data area into multiple segments (first data area and second data area) and performs ECC operations on them sequentially rather than simultaneously. The parity bit storage space is segmented correspondingly, with a first parity bit storage space for the first data area and a second parity bit storage space for the second data area. This segmentation allows the system to maintain comprehensive error correction coverage while significantly reducing the total storage space required for parity bits.
Solution Approach 2:
The patent implements dynamic allocation of ECC resources based on operational needs. The control circuit dynamically switches between performing ECC operations on the first data area and the second data area, and accordingly switches between reading from the first parity bit storage space and the second parity bit storage space. This dynamic approach allows the system to optimize the balance between error correction coverage and storage space utilization.
2Reliability
If ECC area is assigned to all cell arrays, then complete error correction is achieved, but device complexity increases
Solution Approach 1:
The patent segments the ECC area assignment by creating a first ECC area associated with the first data area and a second ECC area associated with the second data area. This segmentation allows the control circuit to manage ECC operations more simply by processing one data area at a time, reducing the overall complexity compared to managing a single large ECC area for all data areas simultaneously.
Solution Approach 2:
The control circuit dynamically manages the ECC area assignment by switching between the first ECC area and the second ECC area based on which data area is currently being processed. This dynamic switching mechanism simplifies the control logic compared to maintaining a static, comprehensive ECC area assignment for all data areas, as it only needs to manage one ECC area at a time.
3Reliability
If parity data is stored for all data areas simultaneously, then all areas benefit from error correction, but storage requirements increase
Solution Approach 1:
The patent segments the storage requirements by creating a first parity bit storage space for the first data area and a second parity bit storage space for the second data area. This segmentation allows the system to store parity data for only one data area at a time, significantly reducing the total storage requirements while still providing error correction coverage for all areas through sequential processing.
Solution Approach 2:
The control circuit dynamically switches between the first parity bit storage space and the second parity bit storage space based on which data area is currently being processed. This dynamic switching allows the system to maintain error correction availability for all data areas while minimizing the total storage space required by only allocating storage for the currently active data area.
Data Source
AI summary
A driving method of a semiconductor device and semiconductor device may be provided. The semiconductor device may include a cell array including a plurality of data areas. The semiconductor device may include an ECC (Error correction Code) area configured to be assigned to only less than all of the data areas at any one time to store parity data corresponding to the data areas.