Semiconductor ECC Architecture for Selective Data and Parity Repair

The patent applies preliminary action by generating error correction codes (ECC) and parity bits in advance before data transmission. The ECC circuit pre-calculates correction values based on the data to be transmitted, and these correction codes are stored alongside the data. When errors occur during high-speed transmission, the pre-prepared correction codes enable immediate error correction without requiring retransmission, thus maintaining high speed while improving reliability.

The patent implements partial action by selectively applying different levels of error correction to different data portions or transmission conditions. The system can adjust the amount of ECC and parity information added based on the specific data importance, transmission channel conditions, and performance requirements. This allows the system to add error correction only where necessary, improving reliability for critical data while maintaining higher efficiency for less critical transmissions.

The patent applies segmentation by dividing the error correction function into separate modular components: an ECC generation circuit that creates correction codes, a parity generation circuit that creates additional check bits, and an ECC correction circuit that performs the actual error correction. Each module handles a specific aspect of error correction, allowing the system to selectively activate different correction mechanisms based on error types and severity. This modular segmentation improves correction efficiency while managing complexity through functional separation.