Semiconductor Memory ECC Test Mode for Error-Pattern Coverage
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Solution Overview
Problem
The increasing bit errors and decreasing yield in DRAMs due to shrinking fabrication design rules necessitate improved reliability and test coverage in semiconductor memory devices.
Innovation Solution
Incorporation of an on-die error correction code (ECC) engine with latches and a control logic circuit that allows for a test mode where the memory cell array connection is cut off, enabling ECC decoding on test data with injected error bits, and providing a severity signal indicating error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods are used, then the memory cell array can be tested, but the ECC engine cannot be independently tested with various error patterns
Solution Approach 1:
The patent segments the testing function by introducing a dedicated test mode that isolates the ECC engine from the memory cell array. In this test mode, the ECC engine can receive test data through a separate path and process error patterns independently, enabling comprehensive testing of the ECC engine without being constrained by the memory cell array structure.
Solution Approach 2:
The patent introduces a test data input mechanism as an intermediary that allows external test data to be fed into the ECC engine during test mode. This intermediary path enables the ECC engine to be tested with various error patterns without requiring direct access to or modification of the memory cell array, thereby improving test coverage while maintaining system integrity.
2Reliability
If the parity check matrix is disclosed during testing, then the ECC engine can be tested, but the security and integrity of the memory system is compromised
Solution Approach 1:
The patent extracts the testing function from the normal operational path by introducing a separate test mode. In this mode, the ECC engine processes test data that is injected through a dedicated path, allowing error correction capabilities to be validated without exposing the internal parity check matrix or other sensitive ECC parameters to external observers.
Solution Approach 2:
Instead of testing the ECC engine by analyzing its normal operational output (which would require disclosing the parity check matrix), the patent inverts the approach by injecting known error patterns into the ECC engine during test mode and verifying its correction capability. This inversion allows comprehensive testing while keeping the parity check matrix confidential.
3Productivity
If fabrication design rules are shrunk, then device density and integration are improved, but bit errors increase and yield decreases
Solution Approach 1:
The patent implements preliminary testing of the ECC engine during manufacturing using the dedicated test mode. By injecting various error patterns into the ECC engine before the memory devices are shipped, manufacturers can verify that the ECC engine correctly identifies and corrects errors, thereby compensating for the increased bit error rates that result from shrunk fabrication design rules.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine and a control logic circuit. The on-die ECC engine includes a first latch and a second latch. The control logic circuit sets the semiconductor memory device to a test mode in response to a first mode register set command. The on-die ECC engine, in the test mode, cuts off a connection with the memory cell array, receives a test data, stores the test data in the first latch, performs an ECC decoding on the test data stored in the first latch and a test parity data, stored in the second latch in response to a read command and provides an external device with a severity signal indicating whether the test data and the test parity data includes at least one error bit and the at least one error bit is correctable.