Semiconductor Die Edge Crack Detection via Voltage Switching
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Solution Overview
Problem
Conventional methods fail to effectively detect minor cracks in semiconductor chip edges, which can become serious and cause failures during manufacturing processes due to thermal, electrical, and mechanical impacts, leading to undetected defects.
Innovation Solution
A semiconductor die with a crack stop structure and edge seal structures biased by different voltages, utilizing a selector circuit to switch between normal and test modes to detect cracks by comparing reference and test currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional crack detection methods are used, then major chip edge cracks can be screened out, but minor cracks cannot be effectively detected
Solution Approach 1:
The detection method is divided into two distinct modes: normal mode for routine operation and test mode for crack detection. This segmentation allows the system to optimize for both operational reliability and detection precision without compromising either function.
Solution Approach 2:
The edge seal structure's bias voltage is dynamically changed between a first voltage (normal mode) and a second voltage (test mode). This dynamic voltage switching enables the system to detect minor cracks by creating potential differences that reveal crack locations through current measurements.
2Reliability
If the edge seal structure is biased by a fixed voltage, then the structure is simple, but crack detection capability is limited
Solution Approach 1:
The bias voltage applied to the edge seal structure is made dynamic rather than fixed. A selector circuit switches between a first voltage during normal operation and a second voltage during test mode, enabling crack detection while maintaining operational simplicity.
Solution Approach 2:
The system periodically switches between normal mode and test mode, applying different voltages at specific intervals. This periodic voltage switching allows crack detection to be integrated into the operational cycle without requiring permanent structural modifications.
3Length of moving object
If thinner grinding is performed to meet stacking demands, then package thickness is reduced, but chip edge cracks occur more frequently
Solution Approach 1:
The crack detection capability is built into the semiconductor die structure itself, allowing cracks to be detected before they cause failures during manufacturing or operation. The edge seal structure with voltage switching provides preliminary detection that prevents defective chips from proceeding to later stages.
Solution Approach 2:
The edge seal structure acts as an intermediary element between the crack stop structure and the IC region. By applying different voltages to this intermediary structure, the system can detect cracks that would otherwise go unnoticed in thin chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method allows for the effective detection of minor cracks in semiconductor chip edges, preventing potential failures by identifying short circuits between the crack stop and edge seal structures, thereby ensuring product quality.
Implementation Method 1
The crack stop structure is biased by a first voltage. The at least one edge seal structure is biased by the first voltage in a normal mode and is biased by a second voltage different from the first voltage in a test mode
Data Source
AI summary
A semiconductor die including a crack stop structure, at least one edge seal structure and a selector circuit is provided. The crack stop structure is located in a periphery region of the semiconductor die. The crack stop structure is biased by a first voltage. The edge seal structure is located between the crack stop structure and an integrated circuit region of the semiconductor die. The edge seal structure is biased by the first voltage in a normal mode and is biased by a second voltage different from the first voltage in a test mode. The selector circuit receives the first voltage, the second voltage and a control signal for placing the semiconductor die in the normal mode or the test mode, and selects and outputs one of the first voltage and the second voltage to the edge seal structure according to the control signal.