Semiconductor Package Edge Interconnects for Direct Die-to-Die Routing
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Solution Overview
Problem
The increasing integration density of semiconductor components poses challenges in connecting integrated circuit dies through interposers alone, requiring innovative solutions to facilitate direct and efficient communication between dies without the need for interposers.
Innovation Solution
The implementation of edge interconnect features, which are conductive lines extending through sealing rings and into scribe line regions, allowing direct connections between neighboring integrated circuit dies without the use of interposers, enabling efficient signal and power supply transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interposers are used to connect integrated circuit dies, then connectivity between dies is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the interposer component from the traditional packaging structure. By forming conductive lines directly through the sealing ring and die structure, the connection function previously performed by the interposer is integrated into the die itself, thereby reducing device complexity while maintaining connectivity.
Solution Approach 2:
The patent merges the interposer's connection function with the die structure by integrating conductive lines directly into the sealing ring region. This consolidation eliminates the need for separate interposer layers and reduces the overall package structure complexity.
2Reliability
If interposers are used to connect integrated circuit dies, then connectivity between dies is achieved, but manufacturing cost increases
Solution Approach 1:
The patent removes the interposer component from the manufacturing process. By forming conductive lines directly through the sealing ring during the die fabrication process, the separate interposer manufacturing, handling, and assembly steps are eliminated, thereby reducing manufacturing cost.
Solution Approach 2:
The conductive lines are formed in advance during the die fabrication process, before packaging. This preliminary formation of connection paths eliminates the need for subsequent interposer assembly steps, reducing manufacturing complexity and cost.
3Reliability
If traditional packaging with interposers is used, then die connections are established, but routing density is limited
Solution Approach 1:
The patent transitions from planar routing through interposer layers to three-dimensional routing through the sealing ring structure. By utilizing the vertical dimension and the annular geometry of the sealing ring, the conductive lines can achieve higher routing density compared to traditional layered interposer approaches.
4Reliability
If interposer layers are used, then die-to-die communication is enabled, but signal transmission efficiency decreases
Solution Approach 1:
The patent extracts the signal transmission path from the interposer medium and creates direct conductive paths through the die structure. This eliminates the additional signal transmission distance and potential signal degradation associated with interposer layers, thereby reducing signal transmission time.
Data Source
AI summary
Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and into scribe line regions. In some embodiments, heterogeneous integrated circuit dies with edge interconnect features are fabricated on the same substrate. Edge interconnect features of the neighboring integrated circuit dies are connected to each other and provide direct connections between the integrated circuit dies without going through an interposer.