Semiconductor Edge Termination Gate Polysilicon Removal
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Solution Overview
Problem
Dielectric breakdown in semiconductor devices, particularly in the edge termination region, due to hole generation and potential defects, affects the reliability and performance of insulated gate bipolar transistors (IGBTs).
Innovation Solution
The implementation of a modified edge termination structure with a discretely provided gate polysilicon layer that reduces the area of polysilicon coverage and increases the thickness of the dielectric film between the gate runner and the circumferential well region, thereby minimizing the risk of dielectric breakdown during device operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate polysilicon layer is provided as a gate runner to connect gate trenches, then the gate structure is completed and electrical connection is achieved, but the polysilicon layer may cause dielectric breakdown due to hole generation and defects in the edge termination region
Solution Approach 1:
The patent removes the gate polysilicon layer from the edge termination region while maintaining it in the active region. This extraction eliminates the source of holes and defects that cause dielectric breakdown in the edge termination area, thereby improving reliability and breakdown voltage without compromising the gate structure's electrical connection functionality
Solution Approach 2:
The patent applies different structural configurations to different regions: the gate polysilicon layer is provided in the active region but omitted in the edge termination region. This local differentiation allows the active region to maintain proper gate control while the edge termination region avoids dielectric breakdown risks, optimizing both regions for their specific functional requirements
2Reliability
If the dielectric film thickness is increased between the gate runner and circumferential well region, then the risk of dielectric breakdown is reduced, but the device area and structural complexity increase
Solution Approach 1:
By removing the gate polysilicon layer in the edge termination region, the patent eliminates the need for additional thick dielectric film structures that would otherwise be required to prevent breakdown. This extraction simplifies the edge termination structure while maintaining high reliability through the inherent elimination of the hole generation source
3Reliability
If the gate polysilicon layer area is reduced in the edge termination region, then the likelihood of defects and breakdown is minimized, but the gate control coverage is reduced
Solution Approach 1:
The patent implements local quality by providing the gate polysilicon layer only in the active region where it is needed for gate control, while omitting it in the edge termination region where it would cause defects. This localized approach maintains adequate gate control coverage in the active area while eliminating defect risks in the edge termination area
Data Source
AI summary
Provided is a semiconductor device including a semiconductor substrate. The semiconductor substrate has: an active portion; and a plurality of gate trench portions provided in the active portion on an upper surface of the semiconductor substrate and extending along an extending direction. The semiconductor device further includes: a gate runner provided between the active portion and an end side of the semiconductor substrate; and a plurality of gate polysilicon disposed apart from each other along the end side and respectively connecting the plurality of gate trench portions to the gate runner.