Semiconductor Edge Region Ion Neutralization for Leakage Reduction
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Solution Overview
Problem
The process of forming semiconductor devices, such as planar MOS transistors or FinFETs, is complicated due to the need for multiple deposition and etching processes to form source/drain doped layers with different ion concentrations, which can lead to tunneling leakage current issues.
Innovation Solution
A method where a base substrate with core and edge regions is used, with first and second gate structures, and source/drain doped layers are formed with first ions in the core region and second ions with opposite conductivity type in the edge region, allowing for simultaneous formation and reducing the ion concentration gradient, thereby avoiding excessive transverse electric fields and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple deposition and etching processes are used to form source/drain doped layers with different ion concentrations, then manufacturing precision is improved, but device complexity increases and tunneling leakage current occurs
Solution Approach 1:
The patent merges the formation of source/drain doped layers in both the core region and edge region into a single deposition process. By using a unified doped layer that covers both regions simultaneously, the invention eliminates the need for separate deposition and etching processes that would otherwise be required to create regions with different ion concentrations, thus reducing fabrication complexity while maintaining precise ion concentration control through selective doping strategies.
Solution Approach 2:
The patent applies local quality by introducing opposite-type ions specifically in the edge region to neutralize excess ions locally. This localized doping approach allows the source/drain doped layer to have different effective ion concentrations in different regions (core vs. edge) without requiring separate layer formations, thereby achieving manufacturing precision while simplifying the overall fabrication process.
2Manufacturing precision
If multiple deposition and etching processes are used to form source/drain doped layers with different ion concentrations, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The patent combines multiple deposition and etching operations into a single deposition process that forms the source/drain doped layer across both core and edge regions simultaneously. This merging of operations significantly reduces the total fabrication time by eliminating redundant process steps while maintaining the ability to achieve different effective ion concentrations through selective ion introduction in subsequent doping steps.
3Reliability
If high ion concentration is used in source/drain doped layer, then conductivity is improved, but transverse electric field increases causing tunneling leakage current
Solution Approach 1:
The patent changes the electrical parameters by introducing opposite-type ions in the edge region to neutralize excess ions. This parameter modification reduces the net ion concentration and thereby decreases the transverse electric field strength in the edge region, effectively suppressing tunneling leakage current while preserving adequate conductivity through the remaining ion concentration.
Solution Approach 2:
The patent converts the potentially harmful high ion concentration in the edge region into a benefit by introducing opposite-type ions that neutralize the excess charge. This transformation reduces the transverse electric field and eliminates tunneling leakage current, while the same doping structure continues to provide necessary conductivity for device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This simplifies the semiconductor device fabrication process while effectively reducing tunneling leakage currents by neutralizing ions in the edge region, ensuring a larger depletion layer width and minimizing leakage issues.
Implementation Method 1
forming a source/drain doped layer in the core region of the base substrate and on both sides of the first gate structure, and in the edge region of the base substrate and on both sides of the second gate structure, respectively, the source/drain doped layer having first ions; doping the second ions in the source/drain doped layer in the edge region
Implementation Method 2
doping the second ions in the source/drain doped layer in the edge region, the second ions having a conductivity type opposite to the first ions
Data Source
AI summary
A semiconductor device and a fabrication method are provided. The fabrication method includes providing a base substrate including a core region having a first gate structure formed thereon, and an edge region having a second gate structure formed thereon; forming a source/drain doped layer, in the core region of the base substrate on both sides of the first gate structure, and in the edge region of the base substrate on both sides of the second gate structure, respectively, the source/drain doped layer including first ions; and doping the second ions in the source/drain doped layer in the edge region, the second ions having a conductivity type opposite to the first ions.