Semiconductor Metallisation Patterning for Edge Thickness Control
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Solution Overview
Problem
Semiconductor devices face a trade-off between low on-resistance (Rds(on)) and mechanical robustness due to the opposing requirements of a thick metallisation layer for electrical performance and a thin layer for mechanical robustness, with dual-layer metallisation techniques being costly and complex.
Innovation Solution
A method that uses a single additional photolithography stage and removal process to achieve varying metallisation layer thicknesses, allowing for full thickness in active areas and reduced thickness in edge areas without additional chemical mechanical planarization (CMP) processing, using selective etching to maintain low Rds(on) and mechanical robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual-layer metallisation techniques are used to satisfy both low Rds(on) and mechanical robustness, then both electrical and mechanical requirements are met, but manufacturing complexity and cost increase due to additional lithography layers and CMP processing
Solution Approach 1:
The invention merges the functions of multiple lithography masks and CMP processing into a single lithography mask design. The first and second metallisation layers are patterned using one lithography mask, eliminating the need for additional lithography layers and CMP steps that would otherwise be required to achieve the same result.
Solution Approach 2:
The single lithography mask serves multiple functions: it defines the patterns for both the first metallisation layer (for low Rds(on)) and the second metallisation layer (for mechanical robustness), as well as establishing the boundary between active and edge termination areas. This multi-functionality reduces the overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of lithography masks required, minimizing the impact on gate resistance while enhancing mechanical robustness and reducing passivation cracks, thus achieving a balance between electrical and mechanical performance.
Implementation Method 1
a layer of metallic material is deposited onto a substrate
Implementation Method 2
masking at least an edge area of the layer with a first lithography mask
Implementation Method 3
removing metal material from the edge area according to the first mask
Data Source
Figure 1A~1B
Figure 2~7
Figure 3
AI summary
A method of manufacturing a semiconductor device is disclosed, and a semiconductor device manufactured with same. A layer of metallic material is deposited onto a substrate, the layer having a top surface. At least an edge area of the layer is masked with a first lithography mask and metallic material is removed from the edge area according to the first mask, whereby a first portion of the edge area has a thickness intermediate the substrate and the layer top surface. The first portion of the edge area is masked with a second lithography mask and metallic material is removed from the first portion according to the second mask, whereby second portions of the edge area are free of deposited metallic material.