Semiconductor Edge Termination with P Pillars for Higher Breakdown Voltage
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Solution Overview
Problem
Conventional high-voltage power semiconductor devices face challenges in achieving uniform electric field distribution and sufficient breakdown voltage due to complex manufacturing processes and large chip area occupation, leading to increased costs and performance limitations.
Innovation Solution
A semiconductor device manufacturing method involving the deposition of an N-drift layer, ion implantation to form P-type pillars, and subsequent epitaxial layers with localized P regions that extend through the N-type epitaxial layer to the field oxide layer, enhancing the surface electric field extension and breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional termination area structure is used, then breakdown voltage can be achieved, but surface electric field extension is narrow and device performance is limited
Solution Approach 1:
The patent introduces a third dimension by forming P-type pillars that extend vertically through the N-drift layer and N-type epitaxial layer to reach the field oxide layer. This vertical dimensionality change enables the electric field to extend deeper into the termination area, effectively increasing the surface electric field extension width without occupying additional chip area.
Solution Approach 2:
The patent applies local quality by creating localized P-type regions with specific doping concentrations (1E16 to 1E18 atoms/cm³) in the termination area, while maintaining different doping characteristics in the active area. The P-type pillars and localized P-type regions provide targeted electric field modulation exactly where needed in the termination area, improving breakdown voltage without affecting active area performance.
2Manufacturing precision
If complicated manufacturing processes with stacked layers are used, then uniform electric field distribution can be achieved, but chip area is occupied and manufacturing cost increases
Solution Approach 1:
Instead of using multiple horizontal stacked layers that occupy chip area, the patent uses vertical P-type pillars extending through the layers to achieve uniform electric field distribution. This vertical approach accomplishes the same electrical function without consuming additional lateral chip area.
Solution Approach 2:
The patent extracts the essential function of electric field modulation from complex stacked layer structures and concentrates it into localized P-type pillars and regions. By taking out only the necessary doping regions, the design achieves uniform electric field distribution without the overhead of complicated multi-layer structures.
3Reliability
If additional ion implantation process is used, then breakdown voltage can be enhanced, but manufacturing cost greatly increases
Solution Approach 1:
The patent merges multiple ion implantation steps into a unified process flow where P-type pillars are formed first, then N-type epitaxial layer is deposited, and finally localized P-type regions are created in the same termination area. This combining of steps into a coordinated sequence reduces the number of separate process modules needed and lowers manufacturing cost.
Solution Approach 2:
The patent applies local quality by creating localized P-type regions with specific doping concentrations (1E16 to 1E18 atoms/cm³) in the termination area, while maintaining different doping characteristics in the active area. The P-type pillars and localized P-type regions provide targeted electric field modulation exactly where needed in the termination area, improving breakdown voltage without affecting active area performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves a uniform electric field distribution, increases breakdown voltage, and improves high-temperature reverse bias reliability by reducing surface electric field peaks, while also reducing manufacturing costs through the reuse of photo resistors.
Implementation Method 1
conducting an ion implant process on the N-drift layer to form a plurality of P-type pillars
Implementation Method 2
depositing a N-type epitaxial layer on the P-type pillars; conducting an ion implant process on the N-type epitaxial layer to form a first P-type epitaxial layer
Implementation Method 3
conducting a field oxidation to the first P-type epitaxial layer to form a second P-type epitaxial layer
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes steps of: depositing an N-drift layer on a substrate, conducting an ion implant process on the N-drift layer to form a plurality of P-type pillars, depositing a N-type epitaxial layer on the P-type pillars, conducting an ion implant process on the N-type epitaxial layer to form a first P-type epitaxial layer and at least one localized P region, conducting a field oxidation to the first P-type epitaxial layer to form a second P-type epitaxial layer, and forming a field oxide layer on the first P-type epitaxial layer and the N-type epitaxial layer. The localized P region passes though the N-type epitaxial layer to the field oxide layer.