Semiconductor Package Edge RDL Layout for Multi-Sided 3D Interconnects
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Solution Overview
Problem
Existing 3D IC integration technologies are limited by single-sided interconnects, which constrain power and signal distribution, leading to scalability issues and suboptimal PPAC (Performance, Power, Area, Cost) optimization.
Innovation Solution
Implementing a semiconductor package with multi-sided interconnects, utilizing edge redistribution layers (RDLs) and through-silicon vias (TSVs) on four side surfaces of 3D IC stacks, enabling skip-die and multi-sided signal and power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If single-sided interconnects are used in 3D IC integration, then device complexity is reduced and ease of manufacture is improved, but power and signal distribution efficiency deteriorates and scalability is limited
Solution Approach 1:
The patent transitions from single-sided (one-dimensional access) interconnects to multi-sided (four-sided) interconnect architecture. Edge RDLs are formed on all four side surfaces of the 3D IC stack, enabling power and signal distribution from multiple directions simultaneously. This dimensional expansion allows skip-die connections and parallel distribution paths, dramatically improving distribution efficiency without complicating the manufacturing process
2Device complexity
If single-sided interconnects are used, then device complexity is reduced, but interconnect lengths increase and design flexibility is constrained
Solution Approach 1:
The interconnect system is segmented into multiple independent edge RDL networks, each located on a different side surface of the 3D IC stack. This segmentation allows different sides to serve different functions (e.g., power on some sides, signals on others) and enables flexible routing configurations. Designers can selectively activate specific edge RDL paths based on application requirements, greatly enhancing adaptability while maintaining manageable complexity
3Productivity
If footprint is increased to improve power and signal distribution, then distribution efficiency improves, but area consumption increases
Solution Approach 1:
Instead of expanding the horizontal footprint to improve distribution, the patent utilizes the vertical and lateral surface dimensions by forming edge RDLs on the four side surfaces of the 3D IC stack. This approach transforms the distribution architecture from a planar expansion to a multi-surface utilization strategy, achieving enhanced distribution efficiency while maintaining a compact footprint
Data Source
AI summary
A semiconductor package includes a plurality of integrated circuit (IC) structures. Each IC structure includes: a first body having a primary surface and a secondary surface, wherein the primary surface is greater than the secondary surface in area; and a primary redistribution layer (RDL) over the primary surface of the first body, with the primary RDL having an edge surface aligned or substantially aligned with the secondary surface of the first body. The semiconductor package further includes an edge RDL over the secondary surface of the first body of each IC structure and the edge surface of the primary RDL of each IC structure. The primary RDL is electrically connected to the edge RDL and the first body, and the edge RDL is electrically connected to the first body through the primary RDL.