Semiconductor Package Edge Seals for Moisture-Resistant Hybrid Bonding
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Solution Overview
Problem
Conventional hybrid bonding interfaces for forming three-dimensional semiconductor structures face challenges in ensuring uniform edge seals, which can lead to moisture ingress and reliability failures due to gaps in the edge seal ring.
Innovation Solution
The implementation of a semiconductor package design that includes multiple edge seals formed by openings coated with sealing materials, such as oxynitride or silicon nitride, and an additional seal provided by a narrow via bar, which electrically couples metal stacks across the hybrid bond interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a uniform array of vias is used in standard hybrid bonding interfaces, then proper height for conductive bonds is ensured, but edge seal uniformity deteriorates leading to gaps and moisture ingress
Solution Approach 1:
The patent divides the via array into two distinct patterns: a first array of vias in the bonding region for conductive bond height control, and a second array of vias in the edge seal region for edge seal uniformity. This segmentation allows each via array to be optimized for its specific function without compromising the other.
Solution Approach 2:
The patent applies different via patterns to different regions of the substrate: a first via pattern with specific spacing and dimensions in the bonding region, and a second via pattern with different spacing and dimensions in the edge seal region. This local differentiation ensures that each region has the quality needed for its specific purpose.
2Productivity
If conventional hybrid bonding interfaces are used, then three-dimensional structures are formed, but moisture ingress occurs due to edge seal gaps
Solution Approach 1:
The patent segments the via array into bonding region vias and edge seal region vias, allowing the edge seal region to have optimized via patterns that ensure continuous sealing without gaps, thereby preventing moisture ingress while maintaining three-dimensional structure formation capability.
Solution Approach 2:
The patent uses a via bar structure that can be selectively removed or modified in the edge seal region after serving its initial purpose in the bonding process, allowing for optimized edge seal formation without compromising the overall three-dimensional structure.
3Ease of manufacture
If edge seal gaps are present, then manufacturing is simpler, but reliability fails due to moisture ingress
Solution Approach 1:
The patent segments the manufacturing process into distinct steps for forming the first via array, forming the second via array, and forming the via bar, allowing each step to be optimized independently. This segmentation enables reliable edge seal formation without significantly complicating the overall manufacturing process.
Solution Approach 2:
The patent performs preliminary actions by forming the first and second via arrays and the via bar before final bonding, ensuring that the edge seal structure is pre-configured to prevent gaps and moisture ingress, thereby improving reliability without adding significant manufacturing complexity.
Data Source
AI summary
Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.