Semiconductor Device Edge Sensing Line Defect Detection
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Solution Overview
Problem
The complexity and diversification of semiconductor device structures complicate the integration of defect sensing elements, leading to increased size and fabrication challenges, particularly during cutting and heating processes that can cause cracks in semiconductor chips.
Innovation Solution
A semiconductor device design that incorporates a first semiconductor chip with a memory cell array and a second semiconductor chip with a peripheral circuit, where sensing lines along the edges of both chips and a detecting circuit in the second chip allow for defect detection without the need for extensive defect sensing elements within the first chip, simplifying fabrication and maintaining defect sensing functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sensing lines are arranged in edge portions of each semiconductor chip to detect defects, then defect detection capability is improved, but device complexity and size increase
Solution Approach 1:
The sensing lines are extracted from the first semiconductor chip and placed only on the second semiconductor chip. The detecting circuit is also placed only on the second chip, separating the sensing function from the memory chip to simplify its fabrication while maintaining defect detection capability for both chips.
Solution Approach 2:
The sensing lines on the second semiconductor chip serve multiple functions: detecting defects in the second chip itself and detecting defects in the first semiconductor chip through the bonding interface. This multi-functionality reduces the need for separate sensing elements on each chip.
2Reliability
If sensing lines are arranged in edge portions of each semiconductor chip to detect defects, then defect detection capability is improved, but the size of semiconductor devices increases
Solution Approach 1:
By extracting the sensing lines from the first chip and consolidating them on the second chip, the total area required for sensing elements is reduced. The sensing lines on the second chip extend to cover both chips' edge portions, eliminating the need for duplicate sensing elements on the first chip.
3Reliability
If extensive defect sensing elements are integrated within the first chip, then defect detection capability is improved, but manufacturing complexity increases during cutting and heating processes
Solution Approach 1:
The sensing lines and detecting circuit are extracted from the first semiconductor chip, which undergoes complex cutting and heating processes. This simplifies the fabrication of the first chip while the sensing function is maintained on the second chip, which has simpler manufacturing requirements.
4Reliability
If sensing lines are placed on both chips, then defect detection coverage is improved, but integration density decreases
Solution Approach 1:
The sensing lines from both chips are merged into a unified sensing system on the second chip. The sensing lines extend along the edge portions of both the first and second chips, creating comprehensive defect detection coverage without requiring separate sensing elements on each chip, thus maintaining integration density.
Data Source
AI summary
A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensing line extending along an edge portion of the first semiconductor chip, an edge portion of the second semiconductor chip, or the edge portion of the first semiconductor chip and the edge portion of the second semiconductor chip; and a detecting circuit in the second semiconductor chip, the detecting circuit being configured to detect defects from the first semiconductor chip, the second semiconductor chip, or both the first semiconductor chip and the second semiconductor chip using the sensing line.