Semiconductor Edge Termination Contact Resistance Control
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Solution Overview
Problem
Conventional semiconductor devices face issues with breakdown voltage in the edge termination region, leading to avalanche current flow and potential destruction during transient voltage events, due to narrow edge termination widths and thin substrate thickness.
Innovation Solution
The semiconductor device incorporates a trench gate structure with strategically placed p+-type contact regions and p++-type surface implantation regions, along with specific contact hole designs and metal films, to increase contact resistance and direct hole current flow through the MOS gates, thereby enhancing avalanche capability and preventing current concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the edge termination width is reduced to increase device integration density, then the device can achieve higher integration, but the breakdown voltage in the edge termination region decreases leading to avalanche current flow and potential destruction
Solution Approach 1:
The patent applies local quality by creating distinct impurity concentration zones within the edge termination region. Specifically, it forms a first semiconductor region with a first impurity concentration and a second semiconductor region with a second impurity concentration that is higher than the first. This localized variation in impurity concentration allows the edge termination region to maintain high breakdown voltage despite reduced width, thereby preventing avalanche current flow while preserving device integration density.
2Volume of moving object
If the substrate thickness is reduced to decrease device size, then the device occupies less space, but the avalanche capability decreases making the device more susceptible to destruction during transient voltage events
Solution Approach 1:
The patent applies parameter changes by systematically varying the impurity concentration parameter across different regions of the semiconductor device. The first semiconductor region has a first impurity concentration while the second semiconductor region has a second impurity concentration that is higher than the first. This parameter variation enhances the avalanche capability of the edge termination region, allowing the device to withstand transient voltage events even when the substrate thickness is reduced for compactness.
3Reliability
If contact resistance is increased to direct hole current flow through MOS gates, then avalanche capability is enhanced, but the ease of current extraction decreases
Solution Approach 1:
The patent applies local quality by creating spatially varying impurity concentrations that strategically control current flow paths. The first semiconductor region with lower impurity concentration and the second semiconductor region with higher impurity concentration work together to both enhance avalanche capability through controlled hole current flow through MOS gates, while the specific geometric arrangement and contact结构设计 maintain ease of current extraction. The local quality variation thus simultaneously addresses both reliability and ease of operation requirements.
Data Source
AI summary
In an edge termination region, in a carrier drawing region between an active region and a gate runner part, a p+-type contact region is provided in a surface region of a p-type well region. In the carrier drawing region, in second contact holes formed an interlayer insulating film, a contact plug is embedded in each via the barrier metal, and contacts of the p+-type contact region and the barrier metal at an emitter electric potential are formed. The contacts of the carrier drawing region are disposed in a striped layout extending along an outer periphery of the active region; the contacts surround the active region. A contact resistance of the contacts of the carrier drawing region is higher than a contact resistance of a contact (emitter contact) of a MOS gate.