Semiconductor Edge Termination With Graded P Layers
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Solution Overview
Problem
Semiconductor devices face challenges in reducing chip area and improving withstand voltage and interruption capabilities at turn-off without deteriorating properties, particularly due to increased current densities and high electric field applications in P layers with high curvature.
Innovation Solution
A semiconductor device configuration with a plurality of impurity layers of a second conductivity type, where surface concentrations increase as they approach the active region, and bottom-end distances are optimized to reduce chip area and enhance voltage resistance and interruption capability by distributing electric fields and reducing edge terminal width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a plurality of P layers are arranged in a region spanning from an edge portion of the active region to an edge portion of a substrate along a substrate surface, then the voltage resistance of the apparatus is increased, but the area of a single chip increases
Solution Approach 1:
The patent applies local quality by creating impurity layers with different impurity concentrations at different locations. Specifically, the first impurity layer has a higher impurity concentration than the second impurity layer, allowing each region to contribute differently to voltage resistance while optimizing space utilization. This gradient structure enables reduced chip area while maintaining voltage resistance characteristics.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 μm.