Semiconductor Edge Termination Layout for Moisture-Resistant Insulation
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Solution Overview
Problem
The insulation reliability of semiconductor devices is compromised due to the deposition of metal oxides or semiconductor oxides when moisture reacts with metal catalysts in high voltage applications, leading to film peeling and the formation of leak paths.
Innovation Solution
A semiconductor device design featuring a peripheral well region of higher impurity concentration than the drift layer, positioned under a covering material, prevents the deposition of foreign substances by ensuring the peripheral end of the well region is inside the covering material's boundary, thus maintaining insulation reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a peripheral well region is formed extending to the peripheral end of the semiconductor substrate, then the electrical field is reduced more effectively, but foreign substances are deposited on the exposed surface leading to film peeling and insulation failure
Solution Approach 1:
The patent applies preliminary anti-action by forming a covering material (such as a protection film or resin seal) that prevents moisture and foreign substances from reaching the peripheral well region and semiconductor substrate surface before the harmful reaction can occur. This proactive coverage eliminates the exposure that would otherwise lead to metal oxide and semiconductor oxide deposition.
Solution Approach 2:
The patent converts the potentially harmful exposed peripheral surface into a beneficial configuration by intentionally designing the peripheral well region to extend beyond the covering material boundary. This allows the high-impurity region to be exposed rather than the vulnerable semiconductor substrate surface, and the covering material is strategically positioned to cover only the critical areas while leaving the peripheral well region accessible, thus preventing film peeling while maintaining electrical field control.
2Object-affected harmful factors
If the peripheral end of the covering material is aligned with the peripheral end of the semiconductor substrate, then the substrate is fully protected, but foreign substances deposit on exposed regions causing leak paths
Solution Approach 1:
The patent applies asymmetry by deliberately misaligning the peripheral end of the covering material with the peripheral end of the semiconductor substrate. The covering material is positioned to end at a location that does not coincide with the substrate edge, creating an asymmetric configuration where the peripheral well region extends beyond the covering material boundary. This asymmetric arrangement ensures that the high-impurity peripheral well region is exposed while the covering material protects the critical semiconductor substrate areas, preventing both moisture exposure and foreign substance deposition on vulnerable surfaces.
Solution Approach 2:
The patent applies local quality by creating different functional zones: the region under the covering material is protected from moisture and foreign substances, while the peripheral well region extending beyond the covering material boundary is designed to handle electrical field control. The covering material is strategically positioned to cover only the areas requiring protection, while leaving the peripheral well region accessible for its electrical function, thus providing localized protection where needed without compromising overall insulation reliability.
3Ease of manufacture
If metal catalysts remain on the semiconductor substrate surface, then the device can be fabricated, but they react with moisture under high voltage to form oxides that cause film peeling and leak paths
Solution Approach 1:
The patent applies the extraction principle by removing or eliminating metal catalysts from the semiconductor substrate surface during the fabrication process. By taking out these harmful metal catalysts before the device is sealed and subjected to humid conditions, the source of the problem is eliminated. This prevents the subsequent reaction between metal catalysts and moisture that would otherwise produce metal oxides causing film peeling and insulation failure, while still allowing the device to be successfully fabricated.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents film peeling and leak path formation, ensuring reliable insulation even in humid environments by containing foreign substance deposition within the well region.
Implementation Method 1
An electrical field is generated when a reverse voltage is applied to a main electrode, but is reduced by a depletion layer formed by a pn junction between the n-type semiconductor layer and the p-type guard ring region.
Implementation Method 2
a depletion layer formed by a pn junction between the n-type semiconductor layer and the p-type guard ring region
Implementation Method 3
metal that is left when the semiconductor device is fabricated and moisture react with each other so that a metal oxide is deposited
Implementation Method 4
semiconductor and moisture react with each other with metal serving as a catalyst so that a semiconductor oxide is deposited due to a strong ionization effect
Implementation Method 5
semiconductor and moisture react with each other with metal serving as a catalyst so that a semiconductor oxide is deposited due to a strong ionization effect
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate having a drift layer of a first conductivity type; an active region in which a main current flows in a thickness direction of the semiconductor substrate; a terminal region of a second conductivity type formed in a surface layer of the drift layer and surrounding the active region; a covering material covering the terminal region; and a peripheral well region of a first conductivity type formed in the surface layer of the drift layer on an outer side of the terminal region and having an impurity concentration higher than that of the drift layer, wherein a peripheral end of the covering material is arranged on an inner side of a peripheral end of the semiconductor substrate, and the peripheral well region is at least partially formed under the covering material and not formed under a peripheral end of the covering material.