Semiconductor Edge Termination for Turn-Off Withstand
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Solution Overview
Problem
Semiconductor devices, such as IGBTs, face challenges in enhancing turn-off withstand capability and reverse recovery performance due to limitations in edge termination structures and lifetime control regions.
Innovation Solution
The semiconductor device incorporates specific conductivity type regions and structures, including first and second conductivity type cathode regions, well regions, floating regions, and lifetime control regions, optimized in arrangement and positioning to improve turn-off and reverse recovery performance by controlling carrier injection and suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional edge termination structure is used, then the device structure is simple, but the turn-off withstand capability is insufficient
Solution Approach 1:
The edge termination structure is segmented into multiple functional regions: a first cathode region extending from the peripheral end toward the active portion, a well region extending in the array direction, and a lifetime control region. This segmentation allows each region to perform its specific function independently, improving turn-off withstand capability through controlled carrier injection and suppression while maintaining a manageable structural complexity.
Solution Approach 2:
Different regions of the semiconductor substrate are assigned different conductivity types and functions: the first cathode region (first conductivity type) suppresses carrier injection at the peripheral end, the well region (second conductivity type) controls the depletion layer, and the lifetime control region manages carrier lifetime. This local differentiation of properties optimizes the turn-off withstand capability at each location without requiring uniform complexity throughout the entire device.
2Reliability
If the first cathode region extends close to the active portion, then carrier injection is suppressed, but the risk of latch-up increases
Solution Approach 1:
The well region acts as an intermediary between the first cathode region and the active portion. It provides a controlled transition zone that allows the first cathode region to extend close to the active portion for effective carrier injection suppression, while the well region's second conductivity type prevents direct interaction that could cause latch-up. The lifetime control region further mediates by managing carrier lifetime in this critical transition zone.
Solution Approach 2:
The conductivity type and carrier lifetime parameters are changed across different regions. The first cathode region has high doping concentration for carrier suppression, the well region has opposite conductivity type to prevent latch-up, and the lifetime control region has optimized carrier lifetime. These parameter variations allow the structure to simultaneously achieve carrier injection suppression and latch-up prevention.
3Reliability
If the lifetime control region extends to the peripheral end, then reverse recovery performance is improved, but the device complexity increases
Solution Approach 1:
The lifetime control region is merged with the existing edge termination structure, combining multiple functions into a single integrated region. It simultaneously provides lifetime control for reverse recovery performance, supports the first cathode region's carrier suppression function, and interfaces with the well region. This merging improves reverse recovery performance without proportionally increasing device complexity.
Data Source
AI summary
To improve the turn-off withstand capability of a semiconductor device. A semiconductor device is provided, including: a semiconductor substrate; an active portion that is provided in the semiconductor substrate and through which current flows between upper and lower surfaces of the semiconductor substrate; a transistor portion provided in the active portion; a diode portion provided in the active portion, and arrayed next to the transistor portion along a predetermined array direction in a top view of the semiconductor substrate; and an edge termination structure portion provided between a peripheral end of the semiconductor substrate and the active portion in the top view. In the top view, at at least part of the edge termination structure portion, which part facing the transistor portion in the direction of extension orthogonal to the array direction, a first-conductivity type first cathode region is provided in contact with the lower surface.