Semiconductor Edge Trench Structure for Crack-Resistant Packaging
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Solution Overview
Problem
Stress during the cutting process of semiconductor devices can lead to cracks in the edge region, compromising the reliability of the semiconductor device.
Innovation Solution
A semiconductor device design featuring a substrate with a semiconductor chip region, a guard ring region, and an edge region, including a trench with distinct bottom surfaces in the edge region to manage stress and prevent crack propagation, along with a wiring structure and interlayer insulating layers to enhance structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the semiconductor device is cut to package the semiconductor device, then the semiconductor device can be packaged, but stress occurs in the edge region causing cracks that deteriorate reliability
Solution Approach 1:
The edge region is segmented into multiple trenches at different depths (first trench, second trench, third trench) rather than a single continuous structure. This segmentation allows stress to be distributed and absorbed at different levels, preventing crack propagation while maintaining the packaging capability
Solution Approach 2:
The trench structure is specifically applied to the edge region where stress concentration occurs during cutting, rather than uniformly across the entire device. The varying depths of trenches (first, second, and third trenches at different levels) provide localized stress management exactly where needed, preserving reliability in the critical edge region while enabling packaging
2Reliability
If a trench structure is added to manage stress, then crack prevention is improved, but device complexity increases
Solution Approach 1:
The complex stress management requirement is resolved by segmenting the trench structure into discrete depth levels (first, second, and third trenches). Each trench serves a specific stress absorption function at its particular depth, making the complex reliability requirement manageable through structured segmentation rather than a single complicated continuous structure
Solution Approach 2:
Instead of adding complexity in the horizontal plane, the trench structure extends into the vertical dimension with multiple depths. The first, second, and third trenches are arranged at different vertical levels, utilizing the depth dimension to manage stress without increasing horizontal complexity, thus improving crack resistance while controlling overall device complexity
Data Source
AI summary
A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.