Semiconductor Package Edge-Via Layout for Compact I/O Routing
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Solution Overview
Problem
As semiconductor chips become smaller and more compact, it becomes difficult to adhere, handle, and test solder balls, and there are challenges in finding mount boards that match the size of the corresponding semiconductor chips, affecting structural stability and electrical utility.
Innovation Solution
A semiconductor package design featuring a semiconductor substrate with a device region and an edge region, including a circuit layer, redistribution layers, and through vias that penetrate the substrate, allowing for improved thermal radiation, increased integration, and enhanced electrical properties by connecting the redistribution layers without occupying the device region, thus enabling more compact and efficient packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If semiconductor chips are made smaller and more compact, then integration density increases, but it becomes difficult to adhere, handle, and test solder balls
Solution Approach 1:
The patent transitions from planar solder ball connections to three-dimensional vertical interconnections through through-vias that penetrate the substrate thickness direction. This dimensional change allows electrical connections to be established without relying on surface-mounted solder balls, thereby maintaining compact chip size while improving handleability and testability through accessible via structures.
Solution Approach 2:
The patent introduces through-vias as intermediary conductive structures that mediate between the circuit patterns on the chip surface and the substrate. These through-vias serve as accessible connection points for handling and testing operations, replacing the difficult-to-access solder balls while maintaining electrical connectivity.
2Quantity of substance
If more I/O pads are integrated into a smaller area, then functional density increases, but structural stability and electrical utility deteriorate
Solution Approach 1:
The patent utilizes the thickness dimension of the substrate to accommodate through-vias that provide robust vertical electrical connections. This three-dimensional connection approach enhances electrical utility and structural stability compared to planar surface connections, allowing higher I/O pad density without compromising reliability.
Solution Approach 2:
The patent segments the connection function into multiple independent through-vias distributed across the substrate. This segmentation provides redundant connection paths, improving structural stability and electrical utility even as the number of I/O pads increases in a compact area.
3Adaptability or versatility
If through vias are used to connect redistribution layers, then integration increases and layout freedom improves, but device region occupancy increases
Solution Approach 1:
The patent applies local quality by positioning through-vias specifically in the edge region rather than uniformly across the device region. This localized placement provides the necessary vertical connections for redistribution layers while preserving the central device region for active circuit elements, thereby maintaining layout freedom without excessive area occupation.
Data Source
AI summary
A semiconductor package includes; a semiconductor substrate including a device region and an edge region, a first redistribution layer on a lower surface of the semiconductor substrate, a second redistribution layer on an upper surface of the semiconductor substrate, through vias vertically penetrating the semiconductor substrate in the edge region to electrically connect the first redistribution layer and the second redistribution layer, and a circuit layer between the lower surface of the semiconductor substrate and the first redistribution layer. The circuit layer may include; a circuit element on the lower surface of the semiconductor substrate, a circuit wiring pattern electrically connected to the circuit element and the first redistribution layer, and a device interlayer dielectric layer substantially encompassing the circuit element and the circuit wiring pattern, wherein the circuit element and the circuit wiring pattern are disposed in the device region and not in the edge region.