Semiconductor EIS Diode Structure for Higher ESD Withstand
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Solution Overview
Problem
The EIS-type diode structure has a low electrostatic withstand capacity, also referred to as ESD withstand voltage, which is inadequate for effectively managing electrostatic discharges.
Innovation Solution
A semiconductor device with an EIS-type diode structure that includes a thyristor structure, comprising specific conductivity type regions and a gate structure, allows for improved electrostatic withstand capacity by managing forward and reverse voltages through the diode and thyristor structures, respectively, with the impurity region and drain region being fixed to the same potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an EIS-type diode structure is used, then the device structure is simple and easy to manufacture, but the electrostatic withstand capacity is low
Solution Approach 1:
The patent combines a diode structure and a thyristor structure into a single integrated device. The diode structure (comprising source region, base region, and drain region) and thyristor structure (comprising source region, base region, collector region, and emitter region) share common regions and are formed in the same semiconductor substrate, allowing the device to benefit from both the simplicity of the diode and the high electrostatic withstand capacity of the thyristor
Solution Approach 2:
The patent creates a multi-functional device that can operate in different modes depending on the applied voltage. The diode structure handles normal forward and reverse voltage operation, while the thyristor structure activates during electrostatic discharge events to provide high-voltage withstand capability. This universal design allows a single device to perform multiple protective functions
Data Source
AI summary
A semiconductor device includes a semiconductor layer of a first conductivity type that has a main surface and that includes a device region, a base region of a second conductivity type that is formed in a surface layer portion of the main surface at the device region, a source region of the first conductivity type that is formed in a surface layer portion of the base region at an interval inward from a peripheral portion of the base region and that defines a channel region with the semiconductor layer, a base contact region of the second conductivity type that is formed in a region different from the source region at the surface layer portion of the base region and that has an impurity concentration exceeding an impurity concentration of the base region, a well region of the first conductivity type that is formed in the surface layer portion of the main surface at an interval from the base region at the device region and that defines a drift region with the base region, a drain region of the first conductivity type that is formed in a surface layer portion of the well region, an impurity region of the second conductivity type that is formed in the surface layer portion of the well region and that is electrically connected to the drain region, and a gate structure that has a gate insulating film covering the channel region on the main surface and a gate electrode facing the channel region on the gate insulating film and electrically connected to the source region and the base contact region.