Semiconductor Device Electrode Height Reduction

Solution Overview

Problem

The existing semiconductor chip stacking technology using through silicon via (TSV) electrodes is limited by the inability to sufficiently reduce the distance between stacked chips due to the thickness of the front surface electrode and resist layers, leading to increased package thickness and reduced chip density.

Innovation Solution

A semiconductor device design featuring a front surface electrode with a reduced thickness and a surrounding resist layer, where the resist layer is strategically removed to lower the electrode height, allowing for closer chip stacking while minimizing damage, and a back surface electrode with a solder layer for electrical connection, enabling reduced inter-chip distance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the front surface electrode and resist layers are made thick to ensure structural integrity and electrical connection, then the reliability of electrical connection is improved, but the distance between stacked chips increases

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoiddistance between chips

Core Design Contradiction:

ReliabilityVSLength of stationary object

Solution Approach 1:

The patent applies parameter changes by reducing the thickness of the front surface electrode from conventional dimensions to 1 μm or less, and optimizing the resist layer thickness to 0.5-2 μm. This parameter optimization maintains electrical connection reliability while significantly reducing the overall height of the electrode structure, enabling closer chip stacking.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies local quality by creating a non-uniform resist layer structure where the resist layer thickness varies at different locations. The resist layer is thicker at the edges (2-5 μm) for structural support and thinner near the center (0.5-2 μm) to reduce overall height. This localized variation maintains structural integrity while minimizing the distance between stacked chips.

Inventive Principle:

Principle #3Local quality

2Productivity

If the electrode height is reduced to decrease package thickness, then the productivity and chip density are improved, but the risk of stacking damage increases

Engineering Contradiction:

Improvechip stacking densityVSAvoidstacking damage

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by creating a non-uniform resist layer structure where the resist layer thickness varies at different locations. The resist layer is thicker at the edges (2-5 μm) for structural support and thinner near the center (0.5-2 μm) to reduce overall height. This localized variation maintains structural integrity while minimizing the distance between stacked chips.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent applies beforehand cushioning by designing the resist layer to extend beyond the electrode edges, creating a protective cushion that absorbs mechanical stress during chip stacking. This protective structure prevents damage to the thin electrode while enabling reduced electrode height for closer chip stacking.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS9922957B2Semiconductor device and method for manufacturing the same

Publication Date: 2018.03.20 KIOXIA CORP

AI summary

A semiconductor device includes a substrate, a first electrode located on an upper surface of the substrate, and a second electrode located on a lower surface of the substrate and electrically connected to the first electrode. The semiconductor device further includes a first resist layer located on the upper surface of the substrate so as to surround the first electrode and spaced from the first electrode, and a second resist layer located on the lower surface of the substrate.