Semiconductor Electrode Layout for Low On-Resistance at Tight Cell Pitch
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving low on-resistance while maintaining a suitable breakdown voltage, particularly due to the trade-off between reducing contact resistance and cell pitch.
Innovation Solution
The semiconductor device design includes a specific structure with a first semiconductor region having a higher impurity concentration than a second region, a conductive portion connected via insulating layers, and a source electrode with multiple contact points, allowing for increased impurity concentration and reduced contact resistance without increasing cell pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cell pitch is reduced to increase device density, then productivity improves, but manufacturing precision deteriorates
Solution Approach 1:
The patent employs preliminary action through selective doping processes where impurity regions are formed in a predetermined sequence. The first semiconductor region with higher impurity concentration is formed first, followed by the formation of the second semiconductor region with lower impurity concentration. This sequential approach allows each doping step to be optimized independently, maintaining manufacturing precision even as device density increases.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a conductive portion, a gate electrode, and a second electrode. The first semiconductor region including a first portion. The second semiconductor region is provided on the first portion. The gate electrode faces the first portion via a gate insulating layer. The second electrode includes platinum, cobalt, or nickel. The second electrode includes a first electrode portion and a second electrode portion. The first electrode portion is arranged with the first portion and the second semiconductor region in the second direction. The first portion is positioned between the first electrode portion and the gate electrode. The second electrode portion is provided on the gate electrode via an insulating layer. The second semiconductor region is positioned between the first electrode portion and the second electrode portion.