Semiconductor Device Electrode Pad Layout Optimization
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing chip size due to restrictions on the layout of electrode pads for wire bonding and wafer-level burn-in (WLBI), which determine the chip size and hinder the benefits of microprocessing.
Innovation Solution
The semiconductor device features electrode pads for wire bonding and WLBI disposed with predetermined spaces along the periphery, allowing constituent elements to be placed between these pads, and includes a test start signal generation circuit and delay circuit to manage acceleration test signals, enabling reduced chip size while maintaining assembly and WLBI restrictions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrode pads are disposed with large spaces to satisfy assembly restrictions and prevent wire contact during plastic molding, then wire bonding reliability is improved, but chip size increases
Solution Approach 1:
The patent segments the electrode pad layout into two distinct types: corner electrode pads disposed in corner regions and non-corner electrode pads disposed in non-corner regions along the periphery. This segmentation allows different spacing rules to apply to different locations, enabling closer spacing in non-corner regions while maintaining adequate spacing in corner regions, thus reducing overall chip size while preserving wire bonding reliability where most critical.
Solution Approach 2:
The patent applies local quality by imposing different spatial constraints on electrode pads based on their location. Corner electrode pads maintain larger spaces to prevent wire contact during molding, while non-corner electrode pads can be disposed with smaller spaces. This localized differentiation optimizes the balance between reliability and chip size by applying strict constraints only where absolutely necessary.
2Productivity
If microprocessing is used to reduce core region size, then integration density is improved, but chip size cannot be reduced correspondingly due to electrode pad layout restrictions
Solution Approach 1:
The patent segments the periphery region into corner and non-corner portions, allowing differential electrode pad spacing. This enables the I/O region to be optimized independently from the core region, permitting aggressive miniaturization in the core while maintaining adequate spacing only where necessary in the periphery, thus achieving both high integration density and reduced overall chip size.
Solution Approach 2:
The patent optimizes electrode pad layout by utilizing the dimensional characteristics of the periphery region differently from the core region. While the core region benefits from two-dimensional miniaturization through microprocessing, the periphery region utilizes the linear arrangement along the chip edges, placing electrode pads at optimal intervals rather than requiring uniform spacing across the entire chip, thereby reducing the area consumed by I/O structures.
3Ease of manufacture
If large spaces are secured between adjacent electrode pads in corner portions, then assembly restrictions are satisfied, but the length of each side of the semiconductor substrate increases
Solution Approach 1:
The patent segments the electrode pad array by location, designating specific corner regions requiring large spaces and non-corner periphery regions allowing smaller spaces. This segmentation concentrates the space requirements to only the necessary corner portions rather than distributing large spaces throughout the entire periphery, thereby minimizing the impact on substrate side length while still satisfying assembly restrictions where they are critical.
Solution Approach 2:
The patent applies local quality by imposing large spacing requirements specifically in corner portions where assembly restrictions are most stringent, while allowing smaller spacing in non-corner periphery regions. This localized application of spacing constraints minimizes the overall area and side length impact while ensuring manufacturability and reliability in the critical corner regions.
Data Source
AI summary
Plural I/O cells (14) having electrode pads for wire bonding (13) are disposed with spaces (55) between them in the vicinity of a corner of an I/O region (11) of a semiconductor substrate (10), and power supply separation cells (16) not to be wire bonded, on which ESD (electrostatic discharge) protection circuits (4) having ESD protection transistors are amounted, are disposed between the respective I/O cells (14), whereby the chip size is reduced upon consideration of layout of the electrode pads.