Semiconductor Electrode Pad Overlap for Chip Size Reduction
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Solution Overview
Problem
The increasing number of electrode pads on semiconductor devices due to enhanced functions and miniaturization of circuit elements leads to a higher area occupancy, constraining chip size reduction, as the stress from inspection probes can damage circuit elements and inhibit the efficient layout of internal circuits.
Innovation Solution
A semiconductor device with a multilayer wiring structure and interlayer insulating films is designed, where the electrode pads overlap with the first circuit region in a planar view, allowing for stress relief and efficient utilization of space by positioning internal circuits under the electrode pads, thereby reducing chip size without compromising circuit integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of electrode pads is increased to support enhanced functions, then the functionality of the semiconductor device is improved, but the chip area occupied by electrode pads increases, inhibiting chip size reduction
Solution Approach 1:
The patent utilizes the vertical dimension by forming circuit elements in the third dimension below the electrode pads through multilayer wiring structures and via holes, transforming a two-dimensional layout problem into a three-dimensional space utilization solution
Solution Approach 2:
The patent implements nesting by placing circuit elements within the vertical space beneath the electrode pads, allowing circuit components to be embedded in the substrate below the pad layer, effectively utilizing unused vertical space
2Area of stationary object
If circuit elements are disposed below electrode pads to reduce chip size, then space utilization is improved, but the stress from inspection probes may damage the circuit elements
Solution Approach 1:
The patent introduces an interlayer insulating film as a mediator between the electrode pads and the circuit elements below, which absorbs and distributes the stress from probe contact, protecting the circuit elements from damage while allowing close proximity placement
Solution Approach 2:
The interlayer insulating film is formed in advance below the electrode pads to create a cushioning layer that prevents stress transmission from probes to the circuit elements, providing protective buffering before any probe contact occurs
Data Source
AI summary
A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.