Semiconductor Electrode Layout for Lower Reverse Recovery Current

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Solution Overview

Problem

Semiconductor devices, such as transistors, face challenges in achieving stable characteristics and efficient carrier evacuation during reverse recovery operations, leading to high reverse recovery current and reduced breakdown strength.

Innovation Solution

The semiconductor device incorporates a specific electrode and wiring member configuration with extended semiconductor regions and insulating members to facilitate efficient carrier evacuation, reducing reverse recovery current and enhancing breakdown strength through controlled potential application.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional electrode and wiring configurations are used, then device structure is simple, but reverse recovery current is high and breakdown strength is reduced

Engineering Contradiction:
Improvebreakdown strengthVSAvoidelectrode and wiring configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The device is divided into multiple functional regions including a first region with a first electrode and second electrode, and a second region with a third electrode. The semiconductor layer is segmented into multiple doped regions (first doped region, second doped region, third doped region) with different conductivity types. This segmentation allows independent optimization of each region for carrier evacuation while maintaining overall device integrity and improving breakdown strength.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the semiconductor layer are doped with different doping concentrations and conductivity types to create local quality variations. The first doped region has a first doping concentration, the second doped region has a second doping concentration, and the third doped region has a third doping concentration. This local quality differentiation enables efficient carrier evacuation in specific regions while maintaining high breakdown strength in other regions.

Inventive Principle:
Principle #3Local quality

2Reliability

If standard semiconductor regions are used, then manufacturing is straightforward, but carrier evacuation efficiency is low

Engineering Contradiction:
Improvecarrier evacuation efficiencyVSAvoidsemiconductor region configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The semiconductor layer is pre-doped with specific doping concentrations and conductivity types in different regions before the reverse recovery operation. The first doped region is prepared with a first doping concentration and conductivity type, the second doped region with a second doping concentration and conductivity type, and the third doped region with a third doping concentration and conductivity type. This preliminary preparation ensures that when reverse recovery occurs, carriers are efficiently evacuated through the pre-configured doped regions without requiring complex real-time control.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12513926B2Semiconductor device and semiconductor module
Publication Date: 2025.12.30 KK TOSHIBA
  • US12513926B2 patent drawing
  • US12513926B2 patent drawing
  • US12513926B2 patent drawing

AI summary

According to one embodiment, a semiconductor device includes first to third electrodes, a first wiring member, a semiconductor member, and an insulating member. The first wiring member includes a first extending portion. A part of the third electrode is between the first electrode and the first extending portion. An other part of the third electrode is between the first and second electrodes. The semiconductor member is provided between the first and second electrodes and between the first electrode and the first extending portion. The semiconductor member includes first to sixth semiconductor regions. The first semiconductor region includes first and second partial regions. The first partial region is located between the first electrode and the third electrode. The insulating member includes the first insulating region. The first insulating region is provided between the third electrode and the semiconductor member.